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08/04/06 rockchip electronics 1 of 128 rock2 data sheet version 1.1 2006-03-07 rockchip electronics
rock2 data sheet v1.1 08/04/06 rockchip electronics 2 of 128 1 features ? 128/100 pins lqfp package ? typical power voltage 3.3v(io), 1.8v(core) ? use one 24mhz crystal oscillator ? 32 gpio (8bits p0,p1,p3,16bits p2) ? 10-bit low resolution adc with 4-channel analog input ? build in stereo 24-bit delta-sigma dac with on-chip headphone amplifier ? build in stereo 16-bit sigma-delta adc (line-in /fm input/ microphone with analog mixer) ? 40 levels digital volume control ? support external codec through i2dsp interface ? support i2c interface ? support usb 2.0 high speed and full speed ? integrated 3 channel dma ? embedded dsp core: ? 4k words boot sync rom ? 128k words sync sram ? 2k words register space for peripherals ? upgradable firmware through usb/flash interface ? memory interface: ? external up to 2(cs) x 64m-2g bytes nand type flash accessed by dma ? support both 8-bit (x8 device) and 16-bit (x16 device) io bus ? support sdram ? support sd/mmc ? support external nor-flash boot up ? video driver: support tft lcd/ oled interface ? pulse width modulators for el backlights ? support watchdog timer ? dsp-based software: ? mpeg1/2/2.5 audio layer 1, 2, 3 decoding, layer3 encoding ? wma 9 decoding ? g.729 based voice recording and playback ? equalizer ? mpeg-4 decoding ? headphone driver output 2x9mw @32 ohm(typ) ; snr: 90db (dac typ) standby leakage current: 25ua low power consumption, <70mw at typical mp3 decoder solution (@12mhz)
rock2 data sheet v1.1 08/04/06 rockchip electronics 3 of 128 2 pin description lqfp128(14x14) pin rock2 lqfp128 v1.1 d4 32 a6 a5 a4 p2.7/a3 fcle/a2 fale/rs/a1 p2.4/a0 p2.3/fce1/sdcs p2.2/sdclk p2.1/sddi p2.0/sddo vcc lcdwrn rd/by fwp fren fwen vdd d7 d6 d5 d1 d3 d2 d0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a7 a12 ba0 ba1 cke clk p2.8/wen p2.9/casn p2.10/rasn p2.11/csn vdd vssd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 vcc p1.1/i2c_sda p1.2/i2c_scl p1.3/i2smclk vcca vddao aol aom aor vssao ail1 air1 ail2 air2 mic vssa vcom iref vdda xin xout vssd vdd dqm0 dqm1 iboot vcca dcdcen lradc1 dcsel dc1_fb1 dc1_fb0 dc0_fb1 dc0_fb0 vccout vddout vregin vregout vbat vcc vssd vdd d15/p3.7 d14/p3.6 d13/p3.5 d12/p3.4 d11/p3.3 d10/p3.2 d9/p3.1 d8/p3.0 fce0 lcdcsn rext100k 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 dp 126 125 124 123 122 121 120 118 117 116 115 114 113 112 111 110 109 128 127 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 rock2 128 pins lqfp package lxvcc lxvdd a10 a9 a8 vsspll vddpll rref agnd dm vdda p1.4/dac_lrck p1.5/adc_lrck p1.6/sdi 119 a11 lcdrdn vssd lradc0 resetn test aoms vcc 33 34 35 36 65 66 67 68 69 70 71 72 106 105 104 103 102 101 100 98 97 108 107 99 p2.13/pwm0 p1.7/sdo ngnd lradc3 lradc2 hp_sense
rock2 data sheet v1.1 08/04/06 rockchip electronics 4 of 128 lqfp100(14x14) pin rock2 lqfp100 v1.1 d4 p2.4/a0 rd/by fwp fren fwen vdd d7 d6 d5 d1 d3 d2 d0 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vcca vddao aol aom aor vssao ail1 air1 ail2 air2 mic vssa vcom iref vdda vssd vdd dc1_fb1 dc1_fb0 dc0_fb0 vddout vregin vregout 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 dp rock2 100 pins lqfp package lxvdd rref agnd dm vdda 75 vssd aoms vcc fale/lcdrs vcc fcle/a2 p2.7/a3
rock2 data sheet v1.1 08/04/06 rockchip electronics 5 of 128 pin & pad descriptions: 128 pin 100 pin pad names pad direction pin description 1 1 vdda p analog 1.8v power output, connect one external 10uf cap 2 2 rref i reference resistor input 3 3 agnd p analog gnd 4 4 dm a i/o usb data minus 5 5 dp a i/o usb data plus 6 6 vcca p analog 3.3v power input 7 7 d0 i/o pull up flash/ lcd/ sdram data bus bit 0 8 8 d1 i/o pull up flash/ lcd/ sdram data bus bit 1 9 9 d2 i/o pull up flash/ lcd/ sdram data bus bit 2 10 10 d3 i/o pull up flash/ lcd/ sdram data bus bit 3 11 11 d4 i/o pull up flash/ lcd/ sdram data bus bit 4 12 12 d5 i/o pull up flash/ lcd/ sdram data bus bit 5 13 13 d6 i/o pull up flash/ lcd/ sdram data bus bit 6 14 14 d7 i/o pull up flash/ lcd/ sdram data bus bit 7 15 15 rd/by i, pull up flash ready/busy signal 16 16 fren o flash read enable 17 17 fwen o flash write enable 18 18 fwp o flash write protect 19 19 vdd p digital core power(1.8v) vssd p digital core ground 20 20 vss p digital ground 21 21 vcc p i/o power(3.3v) 22 22 p2.4/a0 i/o sdram/ sram address bit 0 gpio 23 23 p2.5/a1 i/o sdram/ sram address bit 1 gpio; fale/lcdrs 24 24 p2.6/a2 i/o sdram/ sram address bit 2 gpio; fcle 25 25 p2.7/a3 i/o sdram/ sram address bit 3 gpio 26 x a4 o sdram/ sram address bit 4 27 x a5 o sdram/ sram address bit 5 28 x a6 o sdram/ sram address bit 6 29 x a7 o sdram/ sram address bit 7 30 x a8 o sdram/ sram address bit 8
rock2 data sheet v1.1 08/04/06 rockchip electronics 6 of 128 31 x a9 o sdram/ sram address bit 9 32 x a10 o sdram address bit 10 33 x a11 o sdram address bit 11 sram address bit 10 34 x a12 o sdram address bit 12 sram address bit 11 35 x ba0 o sdram bank address 0 sram address bit 12 36 x ba1 o sdram bank address 1 sram address bit 13 37 x cke o sdram clock enable to sdram 38 x clk o system clock to sdram 39 26 p2.8/wen i/o sdram write enable gpio 40 27 p2.9/casn i/o sdram column address strobe gpio 41 x p2.10/rasn i/o sdram row address strobe gpio 42 x p2.11/csn i/o sdram chip strobe gpio 43 28 p2.13/pwm0 i/o gpio/ pwm output0 44 29 p2.0/sddo i/o sd/mmc data output, rock2 as input connect to sd/mmc sddo 45 30 p2.1/sddi i/o sd/mmc data input, rock2 as output connect to sd/mmc sddi 46 31 p2.2/sdclk i/o sd/mmc clock output 47 32 p2.3/sdcs i/o sd/mmc chip select output 48 33 vcc p i/o power(3.3v) 49 34 vssd p digital ground 50 35 vdd p digital core power(1.8v) 51 36 p0.0 i/o pull up gpio, external int0 52 37 p0.1 i/o pull up gpio, external int1 53 38 p0.2 i/o pull up gpio, external int2 54 39 p0.3 i/o pull up gpio, external int3 55 40 p0.4 i/o pull up & en gpio 56 41 p0.5 i/o pull up & en gpio 57 42 p0.6 i/o pull up & en gpio 58 43 p0.7 i/o pull up & en gpio 59 44 p1.1/ i2c_sda i/o pull up & en gpio, external sda of i2c 60 45 p1.2/ i2c_scl i/o pull up & en gpio, external scl of i2c 61 46 p1.3/ i2smclk i/o pull up & en gpio, i2smclk of external codec 62 47 p1.4 dac_lrck i/o pull up & en gpio, dac lrck of external codec 63 48 p1.5/ i/o gpio, adc lrck of external codec
rock2 data sheet v1.1 08/04/06 rockchip electronics 7 of 128 adc_lrck pull up & en 64 49 p1.6/ sdi i/o pull up & en gpio, sdi data input connect to sdo of external codec 65 50 p1.7/ sdo i/o pull up & en gpio, sdo data output connect to sdi of external codec 66 51 ail1 i l-channel single-end input 1 67 52 air1 i r-channel single-end input 1 68 53 ail2 i l-channel single-end input 2 69 54 air2 i r-channel single-end input 2 70 55 mic i mic single-end analog input 71 56 iref i bias current reference of codec 72 57 vcom i internal biasing voltage for codec 73 58 vssa p negative power supply for codec 74 59 vdda p positive power supply for codec 75 60 aol o l-channel single ended analog output 76 61 vssao p negative power supply to output amplifiers 77 62 aom o common mode analog output 78 63 aoms i common mode sense input 79 64 vddao p positive power supply to output amplifiers 80 65 aor o r-channel single ended analog output 81 x hp_sense i sense of jack insertion 82 66 vdd p digital core power(1.8v) 83 67 vcc p i/o power(3.3v) 84 68 vssd p digital ground 85 x iboot i, pull up boot select, (internal 100k pull up) 86 x dqm0 o sdram dqm0 87 x dqm1 o sdram dqm1 88 69 vddout p dcdc 1.8v output 89 70 lxvdd p dcdc 1.8v switching power input 90 71 vregin p regulator 3.3v voltage input 91 72 vregout p regulator 1.8v voltage output 92 73 dc1_fb0 i nc 93 74 dc1_fb1 i nc 94 75 dc0_fb0 i nc 95 76 dc0_fb1 i nc 96 77 ngnd g power gnd 97 78 vbat p nc 98 79 lxvcc p nc 99 80 vccout p nc
rock2 data sheet v1.1 08/04/06 rockchip electronics 8 of 128 81 dcsel0 i nc 100 82 dcsel1 i nc 101 83 dcdcen i nc vcca p adc 3.3v power input 102 84 vref i adc reference voltage input 103 85 rext100k i adc reference resistor input 104 x lradc3 i low resolution adc input3 105 x lradc2 i low resolution adc input2 106 86 lradc1 i low resolution adc input1 107 87 lradc0 i low resolution adc input0 108 88 vddpll p analog power of pll 109 89 vsspll p analog gnd of pll 110 90 xin i, osc crystal 24mhz osc input pad 111 91 xout o, osc crystal 24mhz osc output pad 112 92 vdd p digital core power(1.8v) 113 93 vssd g digital ground 114 94 vcc p i/o power(3.3v) 115 95 reset i, pull up system reset pin, low enable 116 96 test i, pull down test mode, ( internal 100k pull down) 117 x d8/p3.0 i/o flash/ lcd/ sdram data bus bit 8 gpio 118 x d9/p3.1 i/o flash/ lcd/ sdram data bus bit 9 gpio 119 x d10/p3.2 i/o flash/ lcd/ sdram data bus bit 10 gpio 120 x d11/p3.3 i/o flash/ lcd/ sdram data bus bit 11 gpio 121 x d12/p3.4 i/o flash/ lcd/ sdram data bus bit 12 gpio 122 x d13/p3.5 i/o flash/ lcd/ sdram data bus bit 13 gpio 123 x d14/p3.6 i/o flash/ lcd/ sdram data bus bit 14 gpio 124 x d15/p3.7 i/o flash/ lcd/ sdram data bus bit 15 gpio 125 97 lcdrdn o lcd read execution pin 126 98 lcdwrn o lcd write execution pin 127 99 lcdcsn o lcd driver chip select 128 100 fce0 o flash chip select 0
rock2 data sheet v1.1 08/04/06 rockchip electronics 9 of 128 3 function description 3.1 block diagram dsp flash inte rface i2c interface gpio inte rface 10-bit pll codec usb 2.0 on-chip dc-dc device sd/mmc interface core rom ram on-chip adc xtal , usb phy ( hs & fs ) audio sdram interface i2s interface pwm i/o pin mux rk26xx
rock2 data sheet v1.1 08/04/06 rockchip electronics 10 of 128 3.2 dma rock2 include 3 dma channels. dma0 has a cache of 32bytes. dma1 has a cache of 16bytes. dma2 has a cache of 8bytes, which is adapted to transmitting data between ram and codec. support for memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral- to-peripheral dma transfers support of interrupt enabling and masking 3.2.1 register sar x: source address register for channel x (x=0,1,2) bits name direction reset description 63:32 undefined n/a 0x0 reserved 31:0 sar r/w 0x0 current source address of dma transfer . updated after each source amba transfer. the sinc field in the ctlx register determines whether the address increments, decrements, or is left unchanged on every source amba transfer throughout the block transfer. dar x: destination address register for channel x (x=0,1,2) bits name direction reset description 63:32 undefined n/a 0x0 reserved 31:0 dar r/w 0x0 current destination address of dma transfer . updated after each destination amba transfer. the dinc field in the ctlx register determines whether the address increments, decrements or is left unchanged on every destination amba transfer throughout the block transfer. ctl x: control register for channel x (x=0,1,2)
rock2 data sheet v1.1 08/04/06 rockchip electronics 11 of 128 bits name r/w description 63:45 undefined n/a reserved 44 done r/w done bit if status write-back is enabled, the upper word of the control register, ctl x [63:32], is written to the control register location of the linked list item (lli) in system memory at the end of the block transfer with the done bit set. software can poll the lli ctl x .done bit to see when a block transfer is complete. the lli ctl x .done bit should be cleared when the linked lists are set up in memory prior to enabling the channel. reset value: 0x0
rock2 data sheet v1.1 08/04/06 rockchip electronics 12 of 128 b :32 (see description) block_ts r/w block transfer size . writes this field before the channel is enabled in order to indicate the block size. the number programmed into block_ts indicates the total number of single transactions to perform for every block transfer; a single transaction is mapped to a single amba beat. width: the width of the single transaction is determined by tl x .src_tr_width. reset value: 0x2 31:29 undefined n/a reserved 28 llp_src_en r/w block chaining is enabled on the source side only if the llp_src_en field is high and llp x .loc is non-zero; reset value: 0x0 27 llp_dst_en r/w block chaining is enabled on the destination side only if the llp_dst_e n field is high and llp x .loc is non-zero. reset value: 0x0. 26:25 sms r/w source master select . identifies the master interface layer from which the source device (peripheral or memory) is accessed. 00 = ahb master 1 01 = ahb master 2 24:23 dms r/w destination master select . identifies the the master interface layer where the destination device (peripheral or memory) resides. 00 = ahb master 1 01 = ahb master 2 22:20 tt_fc r/w transfer type and flow control . the following transfer types are supported. ? memory to memory ? memory to peripheral ? peripheral to memory ? peripheral to peripheral 19 undefined n/a reserved 18 dst_scatter_en r/w destination scatter enable bit: 0 = scatter disabled 1 = scatter enabled scatter on the destination side is applicable only when the ctl x .dinc bit indicates an incrementing or decrementing address control. reset value: 0x0 17 src_gather_en r/w source gather enable bit: 0 = gather disabled 1 = gather enabled gather on the source side is applicable only when the ctl x .sinc bit indicates an incrementing or decrementing address control. reset value: 0x0 16:14 src_msize r/w source burst transaction length . number of data items, each of width
rock2 data sheet v1.1 08/04/06 rockchip electronics 13 of 128 ctlx.src_tr_width, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. reset value: 0x1 13:11 dest_msize r/w destination burst transaction length . number of data items, each of width ctlx.dst_tr_width, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. reset value: 0x1 10:9 sinc r/w source address increment . indicates whether to increment or decrement the source address on every source amba transfer. if the device is fetching data from a source peripheral fifo with a fixed address, then set this field to ?no change.? 00 = increment 01 = decrement 1x = no change reset value: 0x0 8:7 dinc r/w destination address increment . indicates whether to increment or decrement the destination address on every destination amba transfer. if your device is writing data to a destination peripheral fifo with a fixed address, then set this field to ?no change.? 00 = increment 01 = decrement 1x = no change reset value: 0x0 6:4 src_tr_width r/w s ource transfer width . mapped to ahb bus ?hsize.? for a non-memory peripheral, typically the peripheral (source) fifo width. this value must be less than or equal to dmah_m x _hdata_width, where x is the amba layer 1 to 4 where the source resides. 3:1 dst_tr_width r/w destination transfer width . mapped to ahb bus ?hsize.? for a non-memory peripheral, typically rgw peripheral (destination) fifo width. this value must be le ss than or equal to dmah_m k _hdata_width, where k is the amba layer 1 to 4 where the destination resides. 0 int_en r/w interrupt enable bit . if set, then all interrupt- generating sources are enabled. reset value: 0x1
rock2 data sheet v1.1 08/04/06 rockchip electronics 14 of 128 cfg x: configuration register fo r channel x (x=0,1,2) bits name direction reset description 63:47 undefined n/a 0x0 reserved 46:43 dest_per r/w 0x0 assigns a hardware handshaking interface (0 -dmah_num_hs_int-1) to the destination of channel x if the cfg x .hs_sel_dst field is 0. otherwise, this field is ignored. the channel can then communicate with the destination peripheral connected to that interface via the assigned hardware handshaking interface. 42:39 src_per r/w 0x0 assigns a hardware handshaking interface (0 -dmah_num_hs_int-1) to the source of channel x if the cfg x .hs_sel_src field is
rock2 data sheet v1.1 08/04/06 rockchip electronics 15 of 128 0. otherwise, this field is ignored. the channel can then communicate with the source peripheral connected to that interface via the assigned hardware handshaking interface. 38 ss_upd_en r/w 0x0 source status update enable . source status information is only fetched from the location pointed to by the sstatarx register, stored in the sstatx register and written out to the sstat x location of the lli if ss_upd_en is high. 37 ds_upd_en r/w 0x0 destination status update enable . 36:34 protctl r/w 0x1 protection control bits used to drive the amba hprot[3:1] bus. 33 fifo_mode r/w 0x0 fifo mode select . determines how much space or data needs to be available in the fifo before a burst transaction request is serviced. 0 = space/data available for single amba transfer of the specified transfer width. 1 = space/data available is greater than or equal to half the fifo depth for destination transfers and less than half the fifo depth for source transfers. the exceptions are at the end of a burst transaction request or at the end of a block transfer. 32 fcmode r/w 0x0 flow control mode . determines when source transaction requests are serviced when the destination peripheral is the flow controller. 0 = source transaction requests are serviced when they occur. data pre- fetching is enabled. 1 = source transaction requests are not serviced until a destination transaction request occurs. in this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the dest ination prior to block termination by the destination. data pre- fetching is disabled. 31 reload_dst r/w 0x0 automatic destination reload . the darx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. a new block transfer is then initiated. 30 reload_src r/w 0x0 automatic source reload . the sarx register can be automatically reloaded from
rock2 data sheet v1.1 08/04/06 rockchip electronics 16 of 128 its initial value at the end of every block for multi-block transfers. a new block transfer is then initiated. 29:20 max_abrst r/w 0x0 maximum amba burst length . 19 src_hs_pol r/w 0x0 source handshaking interface polarity . 0 = active high 1 = active low 18 dst_hs_pol r/w 0x0 destination handshaking interface polarity . 0 = active high 1 = active low 17 lock_b r/w 0x0 bus lock bit . 16 lock_ch r/w 0x0 channel lock bit . 15:14 lock_b_l r/w 0x0 bus lock level . 13:12 lock_ch_l r/w 0x0 channel lock level . 11 hs_sel_src r/w 0x1 source software or hardware handshaking select . this register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel. 0 = hardware handshaking interface. software-initiated transaction requests are ignored. 1 = software handshaking interface. hardware- initiated transaction requests are ignored. if the source peripheral is memory, then this bit is ignored. 10 hs_sel_dst r/w 0x1 destination software or hardware handshaking select . this register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this channel. 0 = hardware handshaking interface. software- initiated transaction requests are ignored. 1 = software handshaking interface. hardware initiated transaction requ ests are ignored. if the destination peripheral is memory, then this bit is ignored. 9 fifo_empty r 0x0 indicates if there is data left in the channel's fifo. can be used in conjunction with cfg x .ch_susp to cleanly disable a channel. 1 = channel's fifo empty 0 = channel's fifo not empty 8 ch_susp r/w 0x0 channel suspend . suspends all dma data transfers from the source until this bit is cleared. there is no guarantee that the current transaction will complete. can also
rock2 data sheet v1.1 08/04/06 rockchip electronics 17 of 128 be used in conjunction with cfg x .fifo_empty to cleanly disable a channel without losing any data. 0 = not suspended. 1 = suspend. suspend dma transfer from the source. 7:5 ch_prior r/w channel number for example: chan0=0 chan1=1 channel priority . a priority of 7 is the highest priority, and 0 is the lowest. this field must be programmed within the following range: 0: (dmah_num_channels ? 1) a programmed value outside this range will cause erroneous behavior. 4:0 undefined n/a 0x0 reserved sgr x: source gather register for channel x bits name direction reset description 63:32 undefined n/a 0x0 reserved. b :20 (refer to description) sgc r/w 0x0 source gather count. source contiguous transfer count between successive gather boundaries. b = log2 (dmah_ch x _max_blk_size + 1) + 19 bits 31: b +1 do not exist and read back as 0. 19:0 sgi r/w 0x0 source gather interval. dsr x: destination scatter re gister for channel x bits name direction reset description 63:32 undefined n/a 0x0 reserved. b :20 (refer to description) dsc r/w 0x0 destination scatter count. destination contiguous transfer count between successive scatter boundaries. b = log2 (dmah_ch x _max_blk_size + 1) + 19 bits 31: b +1 do not exist and read 0. 19:0 dsi r/w 0x0 destination scatter interval.
rock2 data sheet v1.1 08/04/06 rockchip electronics 18 of 128 dmacfgreg: dw_ahb_dmac configuration register bits name direction reset description 63:1 undefined n/a 0x0 reserved 0 dma_en r/w 0x0 dw_ahb_dmac enable bit . 0 = dw_ahb_dmac disabled 1 = dw_ahb_dmac enabled. chenreg: dw_ahb_dmac channel enable register bits name direction reset description 63:8+dnc a undefined n/a 0x0 reserved 7+dnc a :8 ch_en_we w 0x0 channel enable write enable. 7:dnc a, b undefined n/a 0x0 reserved dnc a ?1:0 ch_en r/w 0x0 enables/disables the channel. setting this bit enables a channel, clearing this bit disables the channel. 0 = disable the channel 1 = enable the channel the chenreg.ch_en bit is automatically cleared by hardware to disable the channel after the last amba transfer of the dma transfer to the destination has completed. software can therefore poll this bit to determine when this channel is free for a new dma transfer.
rock2 data sheet v1.1 08/04/06 rockchip electronics 19 of 128 3.2.2 example software _init_dmac2_codec_dac: //chanel 2 mov r6, dmar_sar2 mov r5, 0x00 lda r4, data_table ! _pcm_buffer0 shll.e r4, 1 add r5, 0x02 ! 04 as dram, 02,03 as iram stdu r4, r6, 2 mov r6, dmar_dar2 mov r5, 0x0 mov r4, i2dsp_txdb ! transmit to codec shll.e r4, 1 stdu r4, r6, 2 mov r6, dmar_ctl2 mov r5, 0x10 ! memory to peripheral mov r4, 0x125 ! int enable stdu r4, r6, 2 mov r5, 0x0 mov r4, 2050 ! data length stdu r4, r6, 2 mov r6, dmar_maskblock mov r4, 0x404 st r4, r6 mov r6, dmar_cfg2 ! cfg is 64bits width mov r4, 0x40 mov r5, 0x0 stdu r4, r6, 2 mov r4, 0x1004 ! dist req 2: txreq, [46:43] stdu r4, r6, 2 mov r6, dmar_dmacfgreg mov r4, 0x1 ! enable dma st r4, r6 mov r6, dmar_chenreg mov r4, 0x0404 ! enable channel 2 st r4, r6 ret _init_dmac1_codec_adc: //chanel 1 mov r6, dmar_sar1 mov r5, 0x0 mov r4, i2dsp_rxdb ! read data from codec shll.e r4,1 stdu r4, r6, 2 mov r6, dmar_dar1
rock2 data sheet v1.1 08/04/06 rockchip electronics 20 of 128 mov r5, 0x00 lda r4, data_table1 ! data_table shll.e r4, 1 add r5, 0x04 !04 as dram, 02,03 as iram stdu r4, r6, 2 mov r6, dmar_ctl1 mov r5, 0x20 ! peripheral to memory mov r4, 0x425 ! int enable stdu r4, r6, 2 mov r5, 0x0 mov r4, 2050 ! length stdu r4, r6, 2 mov r6, dmar_maskblock mov r4, 0x202 st r4, r6 mov r6, dmar_cfg1 mov r4, 0x40 mov r5, 0x0 stdu r4, r6, 2 mov r4, 0x0184 ! source req 3: rxreq, [42:39] stdu r4, r6, 2 mov r6, dmar_dmacfgreg mov r4, 0x1 ! enable dma st r4, r6 mov r6, dmar_chenreg mov r4, 0x202 ! enable channel 1 st r4, r6 ret init_dmac: //chanel 0 mov r11, dmar_sar0 mov r1, 0x04 mov r0, 0x6000 stdu r0, r11, 2 mov r11, dmar_dar0 mov r1, 0x10 mov r0, 0x0000 stdu r0, r11, 2 mov r11, dmar_ctl0 mov r1, 0x00 mov r0, 0x24 stdu r0, r11, 2 mov r1, 0x0 mov r0, length stdu r0, r11, 2
rock2 data sheet v1.1 08/04/06 rockchip electronics 21 of 128 mov r11, dmar_cfg0 mov r0, 0x0 mov r1, 0x0 stdu r0, r11, 2 mov r0, 0x04 stdu r0, r11, 2 mov r11, dmar_dmacfgreg mov r0, 0x1 st r0, r11 mov r11, dmar_chenreg mov r0, 0x101 st r0, r11
rock2 data sheet v1.1 08/04/06 rockchip electronics 22 of 128 3.3 usb phy and controller compliant with usb2.0 and usb1.1 specification supports hs (480mbps) / fs (12mbps) modes supports usb suspend state.
rock2 data sheet v1.1 08/04/06 rockchip electronics 23 of 128 3.4 sdram controller supports up to 13 s dram address bits sdram memory data width is 16 supports 2k to 4k rows, 256 to 1k columns, and 2 to 4 banks supports auto refresh with pr ogrammable refresh intervals supports self-refresh supports sdram power-down mode 3.4.1 registers sdram config register (sconr) bits name default description 31:21 unused 20 s_sda_oe_n 1 rev 19 s_sd 0 rev 18 s_scl 1 rev 17:15 s_sa 0 rev 14:13 s_data_width 0 rev 12:9 s_col_addr_width 1000 number of address bits for column address: 15 ? reserved 7-14 ? correspond to 8-15 bits 0-6 ? reserved 8:5 s_row_addr_width 1011 number of address bits for row address: 10-15 ? correspond to 11-16 bits 0-10 ? reserved 4:3 s_bank_addr_width 1 number of bank address bits; values of 0-3 correspond to 1-4 bits, and therefore select 2-16 banks 2:0 unused sdram timing registers the stmg0r and stmg1r registers hold the sdram timing parameters; the sdram controller uses the cas latency value during the initialization sequence in order to program the mode register of the sdram. the user can also specifically force sdram controller to do a mode register update by programming the set_mode_reg bit (bit 9 of sctlr). if you want to change the value of cas latency during normal operation, you should first program the stmg0r ti ming register, and then program bit 9 of sctlr to 1. sdram controller will reset this bit once it has updated the mode register. sdram timing register0 (stmg0r) bits name default description 25:22 t_rc t_rc - 1 0110b active-to-active command period; values of 0-15 correspond to t_rc of 1-16 clocks.
rock2 data sheet v1.1 08/04/06 rockchip electronics 24 of 128 31:27 extended_ t_xsr t_xsr ? 1 00000b 21:18 t_xsr 0111b exit self-refresh to active or auto-refresh command time; minimum time controller should wait after taking sdram out of self-refresh mode before issuing any active or auto-refresh commands; values 0-511 correspond to t_xsr of 1-512 clocks 17:14 t_rcar t_rcar?1 0110b auto-refresh period; minimum time between two auto-refresh commands; values 0-15 correspond to t_rcar of 1-16 clocks. 13:12 t_wr t_wr ? 1 01b for writes, delay from last data in to next precharge command; values 0-3 correspond to t_wr of 1-4 clocks 11:9 t_rp t_rp ? 1 010b precharge period; values of 0-7 correspond to t_rp of 1-8 clocks 8:6 t_rcd t_rcd ? 1 001b minimum delay between active and read/write commands; values 0-7 correspond to t_rcd values of 1-8 clocks 5:2 t_ras_min t_ras_min ? 1 0100b minimum delay between active and precharge commands; values of 0-15 correspond to t_ras_min of 1-16 clocks 26 extended_ cas_latency 1:0 cas_latency cas_latency-1 001b delay in clock cycles between read command and availability of first data 0 ? 1 clock 1 ? 2 clocks 2 ? 3 clocks 3 ? 4 clocks 4,5,6, 7 ? reserved sdram timing register1 (stmg1r) bits name default description 31:22 reserved 21:20 t_wtr t_wtr-1 00b rev for ddr 19:16 num_init_ref num_init_ref - 1 0111b number of auto-refreshes during initialization; values 0-15 correspond to 1-16 auto-refreshes 15:0 t_init t_init 0x0008 number of clock cycles to hold sdram inputs stable after power up, before issuing any commands. sdram control registers you can program sdram control registers at any time after power-up. however, the sdram controller does not poll the registers until the sdram controller finishes current and pending sdram accesses in the write fifo. sdram control register (sctlr) bits name default description 31:18 reserved 17 s_rd_ready_mode 0 sdram read-data-ready mode; set to 1, indicates sdram read data is sampled after s_rd_ready goes active. 16:12 num_open_banks 2 number of sdram internal banks to be open at any time; values of 0-15 correspond to 0-15 banks open
rock2 data sheet v1.1 08/04/06 rockchip electronics 25 of 128 11 self_refresh_status 0 read only. when ?1,? indicates sdram is in self-refresh mode. when ?self_refresh/deep_power_mode? bit (bit 1 of sctlr) is set, it may take some time before sdram is put into self-refresh mode, depending on whether all rows or one row are refreshed before entering self-refresh mode defined by full_refresh_before_sr bit before gating clock in self-refresh mode, ensure this bit is set 10 sync_flash_soft_seq 0 rev 9 set_mode_reg 0 set to 1, forces controller to do update of sdram mode register; bit is cleared by controller once it has finished mode register update 8:6 read_pipe 2 indicates number of registers inserted in read data path for sdram in order to correctly latch data; values 0-7 indicate 0-7 registers 5 full_refresh_after_sr 0 controls number of refreshes done by sdram controller after is taken out of self-refresh mode: 1 ? refresh all rows before entering self-refresh mode 0 ? refresh just 1 row before entering self-refresh mode 4 full_refresh_before_s r 0 controls number of refreshes done before putting sdram into self-refresh mode: 1 ? refresh all rows before entering self-refresh mode 0 ? refresh just one row before entering self-refresh mode 3 precharge_algorithm 1 determines when row is precharged: 0 ? immediate precharge; row precharged at end of read/write operation 1 ? delayed precharge; row kept open after read/write operations 2 power_down_mode 0 forces dw_memctl to put sdram in power-down mode 1 self_refresh/ deep_power_mode 0 forces dw_memctl to put sdram in self-refresh mode. bit can be cleared by writing to this bit or by clear_sf_dp pin, generated by external power management unit 0 initialize 0 forces dw_memctl to initialize sdram; bit reset to 0 by sdram controller once initialization sequence is complete sdram refresh interval register (srefr) bits name default description 31:24 gpi - rev 23:16 gpo 0 rev 15:0 t_ref 100 clocks, assuming a refresh period of 7.8us, at system frequency of 12mhz number of clock cycles between consecutive refresh cycles; address mask registers (smskr0) bits name default description 31:11 reserved
rock2 data sheet v1.1 08/04/06 rockchip electronics 26 of 128 10:8 reg_select reg_select n 000b register determines which timing parameters of memory connect to associated chip select; primarily used for specifying static memories 0 ? register set 0 1 ? register set 1 2 ? register set 2 7:5 mem_type chip_select n _mem 000b type of memory connected to corresponding chip select: 0 ? sdram, others ? reserved 4:0 mem_size block_size n 0x0b size of memory connected to corresponding chip select; 0 ? no memory is connected to the chip select 1 ? 64kb 2 ? 128kb 3 ? 256kb 4 ? 512kb 5 ? 1mb 6 ? 2mb 7 ? 4mb 8 ? 8mb 9 ? 16mb 10 ? 32mb 11 ? 64mb 12 ? 128mb 13 ? 256mb 14 ? 512mb 15 ? 1gb 16 ? 2gb 17 ? 4gb 3.4.2 programming sequence program the sdram controller regist ers using the following sequence: - sdram mask registers (smskr) program mask register - sdram bank address, row/column address and data width (sconr) program sdram configuration register - sdram timing parameters (stmg0r) program sdram timing register0 - the remaining sdram timing parameters (stmg1r) program sdram timing register1 - refresh period (srefr) program sdram refresh interval register - sdram control register (sctlr). set the "initialize" bit for the controller - to do auto sdram initialization sequence. since setting the "initialize" - bit starts the sdram initialization sequence, this register should be - programmed last program sdram control register 3.4.3 sdram controller functional power-on initialization the sdram controller follows the jedec-recommended sdr-sdram power-on initialization sequence as follows: 1. apply power and start clock; maintain a nop condition at the inputs 2. maintain stable power, stable clock, and nop input conditions for a minimum of t_init clock cycles 3. issue precharge commands for all banks of the device 4. issue auto-refresh commands, depending on the value num_init_ref in the programmable register 5. issue a set-mode register command to initialize the mode register the sdram controller performs a power-on sequence of the sdram under these circumstances: immediately after reset when the programmable initialize bit (bit 0 of sctlr) is set, the sdram controller resets the bit when it comes out of initialization. all sdram read/write requests that occur during initialization are queued in the memory controller. figure 16 illustrates the commands issued to the sdram by th e controller during the power-on initialization.
rock2 data sheet v1.1 08/04/06 rockchip electronics 27 of 128 figure 16: sdr-sdram power-on command sequence the t_init, t_rp, and t_rcar compile-time parameters are the default values for t_init, t_rp and t_rcar, respectively, which you can use for initialization. if you feel that the reset time of the system is long enough to take care of the t_init time, then you can assign a value of zero to the t_int parameter. the sdram controller initializes the sdram after rese t using the specified default compile-time timing parameters. after reset, if you feel that these timing parameters are not adequate, then you can program the timing parameters accordingly and then program the initialize bit ? that is, bit 0 of sctlr ? to 1. this forces the sdram controller to initialize the sdram. the t_mrd is fixed at a value of 3 clock cycles, according to the jedec standard. set-mode register the dw_memctl automatically sets the sdr-sdram mode register and extended-mode register (extended-mode register is only for mobile-sdram) during the power-up initialization. during normal operation, if you want to set the mode register or extended-mode register, you need to set set_mode_reg (bit 9 of sctlr) in the control register (sctlr) to 1. after the memory controller finishes the mode register setting, it clears the set_mode_reg bit to 0. the ?burst length? field and the ?burst type? field of the sdr-sdram-mode register are fixed by the dw_memctl to ?010? (burst length 4) and ?0? (sequential burst), respectively. the dw_memctl programs the ?cas latency? field and the ?operating mode? field of the mode register according to the values provided by the user in the control and timing registers. read/write operations the dw_memctl converts all ahb bursts to 4-word bursts on the sdram side. the memory bursts are concatenated to achieve continuous data flow for long ahb bursts. you can terminate the memory read/write
rock2 data sheet v1.1 08/04/06 rockchip electronics 28 of 128 burst with either a precharge command or terminate command, depending on which precharge mode ? immediate precharge or delayed precharge ? that you program. you can also terminate the write burst with a sub sequent write burst. the dw_memctl does not use auto-precharge mode. the dw_memctl supports two precharge modes ? immediate precharge and delayed precharge. if you program for an immediate precharge mode, then the dw_memctl closes the open row after a read or write access. if you program for a delayed precharge mode, then the dw_memctl keeps the row open after an access. the dw_memctl can keep multiple banks open at the same time, depending on the value of num_open_bank in the programmable register. when the number of open banks reaches the num_open_bank and an access to a new bank comes, the dw_memctl will close the oldest bank (the bank opened first) before opening the new bank. example of register setting: sdram register setup (k4s640832d) 32`h0001bc54, smskr0 = 32`h00b 32`h0001bc00, sconr = 32`h1c1168 32`h0001bc04, stmg0r = 32`h19d9451 (or 32`h1ddd696?) 32`h0001bc08, stmg1r = 32`h70008 32`h0001bc10, srefr = 32`h3e8 (for 100mhz clock) 32`h0001bc0c, sctlr = 32`h9 (or 20009) 3.4.4 example software init_sdram: mov r0, mempcr mov r1, 0x03 st r1, r0 mov r0, memctl_sconr mov r2, 0x1168 mov r3, 0x1c stdu r2, r0, 2 mov r0, memctl_stmg0r mov r2, 0x9451 mov r3, 0x19d stdu r2, r0, 2 mov r0, memctl_stmg1r mov r2, 0x08 mov r3, 0x7 stdu r2, r0, 2 mov r0, memctl_srefr mov r2, 0x3e8 mov r3, 0x0 stdu r2, r0, 2 mov r0, memctl_sctlr mov r2, 0x2009 mov r3, 0x0 stdu r2, r0,2
rock2 data sheet v1.1 08/04/06 rockchip electronics 29 of 128 3.5 flash / video controller the ex_memctl is an ahb slave in rock2 and provides all the functionality for read/write transactions from multip le ahb masters to the off-chip memory device. asynchronous interface is supported. the ex_memctl include a register file, an ecc calculator and external interface. the external interface accessible space is logically segmented into lcd interface region, flash/ide interface region, cf card interface region. lcd interface have 256 word space co rresponds a chip select named lcdcs. flash and ide interface have 256word spac e which split into two chip selects named fmcs0, fmcs1. cf card interface have 2kword space corresponds a chip select named cfcs. the ex_memctl also include a store buffer to help prevent pipeline stalls during stores to external memory. the ex_memctl interfaces share address, data and write/read control pins, except flash/ ide interface have a set of indicate control pins which include ale, cle, wp, fwr, frd, rdy. asynchronous interface is supported. ecc calculator supports 8bit and 16bit external device supports four chip select line: fmcs0, fmcs1, cfcs, lcdcs supports up to 11 address line the wait cycles inserted can be programmed or corresponded to the hardware input control signal-rdy the external interface signals are: madder[13:0] external memory address bus output this bus contains the address for external memory accesses. during internal memory accesses, the madder[13:0] pins retain their previous state. the actual address signal output is the alternative of madder[13:0] and sdram s_addr[ba1,ba0,a11:0]. rdata[15:0] external memory interface input data bus input this bus is the data bus for external memory and external memory-mapped peripheral read. wdata[15:0] external memory interface output data bus output this bus is the data bus for external memory and external memory-mapped peripherals write. the actual data signal output is the alternative of wdata[15:0] and sdram s_wdata[15:0]. epcsn data memory chip select output the chip selects enable off-chip expansion for memory space corresponding to eprom region. rock2 asserts the chip select for the duration of the external access based upon the address space being accessed. the values set in the uwait registers determine the timing of these signals. cfcsn timing is relative to the rdn and wrn strobes. fmcs[1:0]n memory-mapped peripheral chip selects output these chip selects provide decoded selects for memory-mapped peripherals residing in external memory space. rock2 asserts the appropriate chip select for the duration of the external access based upon the address space being accessed. the values set in the fmwait registers determine the timing of these signals. fmcs[1:0]n timing is relative to the fmrdn and fmwrn strobes. lcdcsn memory-mapped peripheral chip select output
rock2 data sheet v1.1 08/04/06 rockchip electronics 30 of 128 these chip selects provide decoded selects for memory-mapped peripherals residing in external memory space. rock2 asserts the appropriate chip select for the duration of the external access based upon the address space being accessed. the values set in the lcdwait registers determine the timing of these signals. lcdcsn timing is relative to the rdn and wrn strobes. wrn write strobe output rock2 asserts this active-low write strobe for external memory writes normally. the wrn signal is an invert version when both cfcsn asserts and the bit wrp in sysctl register is set to ?1?. rdn write strobe output rock2 asserts this read strobe during external memory reads. fmwrn write strobe output rock2 asserts this active-low write strobe fo r external peripherals flash segment writes. fmrdn write strobe output rock2 asserts this read strobe during external peripherals flash segment reads. fmcle flash command latch enable output the fmcle output signal is connected to nand flash memory device cle input. this signal is assert active- high during an operation write to external peripherals flash segment base address +02. fmale flash address latch enable output the fmale output signal is connected to nand flash memory device ale input. this signal is assert active- high during an operation write to external peripherals flash segment base address +04. fmwp flash write protect output the fmwp output signal is connected to nand flash memory device wpn input. this signal active-low provides inadvertent write/erase protect during power transitions. rdy hardwire wait state pull-up input rock2 samples this signal and then appropriately set the bit rdy ?1? or ?0? in the fmst register. lcdrs lcd register select output the lcdrs output signal indicate a operation to the lcd register. this signal is assert active-high during accesses to external peripherals lcd segment base address +02. the signal also assert even ex_ctl accept a external memory operation at address over than 0x02_8000. m_dout_valid data write out valid output ex_memctl valid signal for write data to external memory; de cides direction of data flow all bits are identical; one bit per byte of data provided to improve drive strength, routing, and timing closure muxsel mux select output address signal mux and write data signal mux select input. registers: register description address r/w default ecc0 ecc result0 +00 r _ ecc1 ecc_result1 +04 r _ ecc2 ecc_result2 +08 r _ ecc3 ecc_result3 +0c r _ eccctl ecc control register +10 w eccst ecc status register +14 r fmctl flash chip select control register +18 w fmst flash memory status ready indicate +1c r cfwait cf card memory region wait state +20 r/w fmwait flash memory wait state +24 r/w lcdwait lcd interface wait state +28 r/w sysctl system control register +2c w
rock2 data sheet v1.1 08/04/06 rockchip electronics 31 of 128 ecc result register 32 24 16 8 0 res ecc0 res reserved this bits are reserved ecc0 ecc result 0 the current ecc result 32 24 16 8 0 res ecc1 res reserved this bits are reserved ecc1 ecc result 1 the 1st backuped ecc result 32 24 16 8 0 res ecc2 res reserved this bits are reserved ecc2 ecc result 2 the 2nd backuped ecc result 32 24 16 8 0 res ecc3 res reserved this bits are reserved ecc3 ecc result 3 the 1th backuped ecc result after 512byte data had complete, the content of ecc2 is copied to ecc3, ecc1 is copied to ecc2 and ecc0 is copied to ecc1,and then the result of ecc will save into the register ecc0. ecc control register 32 13 12 11 8 7 4 3 2 1 0 res region addrh addrl epd rdn x16 erst res reserved this bits are reserved region select the ecc active region 00: cf card region 01: flash memory region 10: lcd device region 11: register file region addrh(l) select the ecc active range the ecc should be activing when access in range addrl to addrh. epd ecc power down the ecc will power down when this bit is set rdn indicate data flow direction 0:data direction as output 1: data direction as input x16 data bus width 0:data width is 16 1:data width is 8
rock2 data sheet v1.1 08/04/06 rockchip electronics 32 of 128 erst ecc reset this bit resets the ecc. when set, the ecc clear all the result and then operate restart and this bit will auto cleared. ecc stutus register 32 1 0 res erdy res reserved this bits are reserved erdy flash ready indicate 0:ecc is busy 1:ecc is ready flash memory control register 32 2 1 0 res fsel fcs0 res reserved this bits are reserved fcs0 flash memory chip select control 1:hold flash memory chip select activity 0:flash memory chip select activity free fsel flash memory chip select pin selection 1:select chip1 (pin fmcs1n) 0:select chip0 (pin fmcs0n) flash memory stutus register 32 1 0 res wp rdy res reserved this bits are reserved rdy flash ready indicate 0:flash is busy 1:flash is ready this bit is the sample of pin fmrdy. wp flash write protect 0:flash program/erase disable 1:flash program/erase enable this bit is out put to the pin fmwp epwait state register 32 15 12 11 10 5 4 0 res csrw rdy rwpw rwcs rdy hardware ha ndshaking controller bit when this bit is set to ?1?, an external device asserts signal ?rdy? to extend a wait-state access and the rest bits in this register will be ignored. csrw chip select to r/w strobe leading edge this field specifies the number of processor clock cy cles from the falling edge of cfcsn to the falling edge of rdn or wrn. if this bit is set to 0x0, the processor uses a csrw value of 0x1. rwpw r/w pulse width this field controls the width of rdn or wrn in processor clock cycles. if this bit is set to 0x0, the processor uses an rwpw value of 0x1. rwcs r/w strobe to enable deassertion [4:0] this field specifies the number of processor clock cycles from the rising edge of rdn or wrn to the rising edge of cfcsn. if this bit is set to 0x0, the processor uses an rwcs value of 0x1. rwcs r/w strobe to enable deassertion
rock2 data sheet v1.1 08/04/06 rockchip electronics 33 of 128 this field specifies the number of processor clock cycles from the rising edge of rdn or wrn to the rising edge of cfcsn. if this bit is set to 0x0, the processor uses an rwcs value of 0x1. fmwait state register 32 15 12 11 10 5 4 0 res csrw rdy rwpw rwcs rdy hardware ha ndshaking controller bit when this bit is set to ?1?, an external device asserts signal ?rdy? to extend a wait-state access and the rest bits in this register will be ignored. csrw chip select to r/w strobe leading edge this field specifies the number of processor clock cycles from the falling edge of fmcs[1:0]n to the falling edge of fmrdn or fmwrn. if this bit is set to 0x0, the processor uses a csrw value of 0x1. rwpw r/w pulse width this field controls the width of fmrdn or fmwrn in processor clock cycles. if this bit is set to 0x0, the processor uses an rwpw value of 0x1. rwcs r/w strobe to enable deassertion [4:0] this field specifies the number of processor clock cycles from the rising edge of fmrdn or fmwrn to the rising edge of fmcs[1:0]n. if this bit is set to 0x0, the processor uses an rwcs value of 0x1. rwcs r/w strobe to enable deassertion this field specifies the number of processor clock cycles from the rising edge of fmrdn or fmwrn to the rising edge of fmcs[1:0]n. if this bit is set to 0x0, the processor uses an rwcs value of 0x1. lcdwait state register 32 15 12 11 10 5 4 0 res csrw rdy rwpw rwcs rdy hardware ha ndshaking controller bit when this bit is set to ?1?, an external device asserts signal ?rdy? to extend a wait-state access and the rest bits in this register will be ignored. csrw chip select to r/w strobe leading edge this field specifies the number of processor clock cy cles from the falling edge of lcdcsn to the falling edge of rdn or wrn. if this bit is set to 0x0, the processor uses a csrw value of 0x1. rwpw r/w pulse width this field controls the width of rdn or wrn in processor clock cycles. if this bit is set to 0x0, the processor uses an rwpw value of 0x1. rwcs r/w strobe to enable deassertion [4:0] this field specifies the number of processor clock cycles from the rising edge of rdn or wrn to the rising edge of lcdcsn. if this bit is set to 0x0, the processor uses an rwcs value of 0x1. rwcs r/w strobe to enable deassertion this field specifies the number of processor clock cycles from the rising edge of rdn or wrn to the rising edge of lcdcsn. if this bit is set to 0x0, the processor uses an rwcs value of 0x1. system control register 32 3 2 1 0 res fmwrp wrp sisel res reserved this bits are reserved sisal sdram interface select 0:ex_memctl external interface signal assert 1:dw_memctl sdram interface signal assert this bit control the output level of selsdram. signal selsdram control the output address bus mux and data bus mux. wrp wrn and rdn signal polarity 0:wrn and rdn signal normal output 1:invert wrn and rdn signal this bit specifies the polarity for the wrn and rdn signal. fmwrp fmwrn and fmrdn signal polarity 0:wrn and fmrdn signal normal output
rock2 data sheet v1.1 08/04/06 rockchip electronics 34 of 128 1:invert fmwrn and fmrdn signal this bit specifies the polarity for the wrn and rdn signal.
rock2 data sheet v1.1 08/04/06 rockchip electronics 35 of 128 3.6 wdt 3.6.1 registers wdt_cr: control register bits name direction description 31:5 n/a n/a reserved and read as zero (0). 4:2 rpl r/w reset pulse length. writes have no effect as wdt_hc_rpl is 1, these bits are read-only, which is equals to 011. the reset pulse length is 16 pclk cycles. 1 rmod r/w response mode. selects the output response generated to a timeout. 0 = generate a system reset. 1 = first generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset. 0 wdt_en r/w wdt enable. this bit is used to enable and disable the wdt. when disabled, the counter does not decrement. thus, no interrupts or system resets are generated. once this bit has been enabled, it can be cleared only by a system reset. 0 = wdt disabled. 1 = wdt enabled. reset value: 0 wdt_torr: timeout range register bits name dir. description 31:8 n/a n/a reserved and read as zero (0). 7:4 top_init r/w timeout period for initialization. reset value: fixed at zero. 3:0 top r/w timeout period. (set to 0x07 for normal use, verify for 0x0) the range of values is limited by 7. the range of values available for a 32-bit watchdog counter are: where i = top and t = timeout period for i = 0 to 7 t = 2(16 + i) reset value: 7
rock2 data sheet v1.1 08/04/06 rockchip electronics 36 of 128 wdt_ccvr: current co unter value register bits dir. description 22:0 r this register, when read, is the current value of the internal counter. reset value: 7f ffff wdt_crr: counter restart register bits direction description 31:8 n/a reserved and read as zero. 7:0 w this register is used to restart the wdt counter. as a safety feature to prevent accidental restarts, the value 0x76 must be written. a restart also clears the wdt interrupt. read ing this register returns zero. reset value: 0 wdt_stat: interrupt status register bits direction description 31:1 n/a reserved and read as zero. 0 r this register shows the interrupt status of the wdt. 1 = interrupt is active regardless of polarity. 0 = interrupt is inactive. reset value: 0 wdt_eoi: interrupt clear register bits direction description 31:1 n/a reserved and read as zero. 0 r clears the watchdog interrupt. this can be used to clear the interrupt without restarting the watchdog counter. reset value: 0 3.6.2 operation flow 1 select required timeout period at wdt_torr. 2 set reset pulse length, response mode, and enable wdt at wdt_cr. 3 3 write 0x76 to wdt_crr(counter restart register). 4 starts back to selected timeout period. 5 can clear by reading wdt_eoi (interrupt cl ear register) or restarting (kicking) the counter by writing 0x76 to wdt_crr (counter restart register).
rock2 data sheet v1.1 08/04/06 rockchip electronics 37 of 128 3.6.3 example software mov r0, wdt_torr ! normal use: 0x7, test it: 0x0 mov r2, 0x7 ! 2**(16+7)=8,388,608 cycles generate wdt interrupt, st r2, r0 ! 2**(16+8)=16,777,216 cycles generate wdt reset mov r0, wdt_cr ! [1]: first generate an wdt interrupt; [0]:enable mov r2, 0x0f st r2, r0 mov r0, wdt_crr !0x76, clear the counter mov r2, 0x76 st r2, r0 ????. (a period of program) mov r0, wdt_crr !0x76, clear the counter mov r2, 0x76 st r2, r0
rock2 data sheet v1.1 08/04/06 rockchip electronics 38 of 128 3.7 clock generator 3.7.1 overview ? input frequency : 24 mhz. ? programmable frequency divider ? generate the dsp frequency mclk, frequency range : 12mhz ? 80mhz. ? generate the codec frequency i2smclk, 12mhz ? generate the usb 12mhz clock, ahb clock, apb clock, sd/mmc card clock ,adc clock, pwm clock mclk, hclk, pclk ??? clock ?? ??? pllvco (clk_out): 360mhz mclk: 80mhz hclk: 80mhz pclk: 50mhz usb12m: 12mhz i2smclk: 12mhz adcclk: 12mhz pwm count_clk: 1mhz sdciclk: 50mhz gpio 50mhz clk_30_60: 30mhz
rock2 data sheet v1.1 08/04/06 rockchip electronics 39 of 128 3.7.2 block diagram figure 1 shows a block diagram of the clock generator. an external crystal clock is connected to the oscillation amplifier, and the pll (phase-locked-loop) converts the low input frequency into a high-frequency clock clk_out required by rock2. and then divide frequency clk_out to the needed clocks.
rock2 data sheet v1.1 08/04/06 rockchip electronics 40 of 128 3.7.3 block i/os adc controller i/o description register file interface n[5:0] i 5-bit input divider control to pll m[8:0] i 9-bit feedback divider control to pll od[1:0] i output divider control signal to pll bp i bypass pll signal to pll clk_out o pll adjustable clock output pd i disable power down mode mclkcon[7:0] i 8-bit divider control to mclk i2smclkcon[7:0] i 8-bit divider control to i2smclk i2smclk_en i i2smclk output enable i2smclk_sel i i2smclk output select ahbclkcon[1:0] i 2-bit divider control to ahb apbclkcon[1:0] i 2-bit divider control to apb memctrlclk_en i dma clock enable dmaclk_en i dma clock enable sdclk_en i sdciclk output enable usbclk_en i usb12m clock output enable adc_sel[2:0] i 3-bit divider control to adc clock reference to adc module tapre[9:0] i 10-bit divider control to pwm clock reference to pwm module register file interface i/os total: application interface mclk o main clock for dsp i2smclk o i2s main clock usb12m o 12mhz clock for usb hclk o ahb clock pclk o apb clock adcclk o adc clock count_clk o pwm clock application i/os total: # control interface clk_in i external oscillator clock input
rock2 data sheet v1.1 08/04/06 rockchip electronics 41 of 128 pll i/o description pll i/o interface oe1=1 i disable clk1 oe2=1 i disable clk2 oe=0 i enable clk_out reset i in normal mode, reset=0, when in test mode 0, set to external ~reset mode pll_tst[1:0] i test signal to pll 3.7.4 divider timing characteristics figure 2. divider timing characteristics ?????? ????????? ?? 0 ????? ????????? enable ?? 0 ??? ?? 0 ??????
rock2 data sheet v1.1 08/04/06 rockchip electronics 42 of 128 3.7.5 main clock generate : clk generate: osc (24mhz) n=17, m=128: 24mhz/ 1 7x128=180.706mhz n=25, m=128: 24mhz/25x128=122.88mhz fvco/(p*q) = i2smclk, t=mclk_div+1, p*q= i2smclk_div+1 note: when use 256 x32k, p*q = 15 ( ? n m p*q ?????? n-2 m- 2 p*q-1) clk generate: osc (24mhz) fvco [mhz] t mclk(dsp) [mhz] p q i2smclk [khz] 2 256 x 44.118k 4 256 x 22.059k n=17 m=256 361.412m 6 60.235 p=16 22.588m 8 256 x 11.028k 4 45.176 2 256 x 44.118k 6 30.118 4 256 x 22.059k 8 22.588 8 256 x 11.028k 10 18.071 12 15.059 n=17 m=128 180.706m 14 12.908 p=8 22.588m 1 256 x 96k 2 256 x 48k, 384 x 32k 3 256 x 32k 4 256 x 24k, 384 x 16k 6 256 x 16k n=25 m=256 245.76m 6 40.96 p=10 24.576m 12 256 x 8k 2 61.44 1 256 x 96k 4 30.72 2 256 x 48k, 384 x 32k 6 20.48 3 256 x 32k 8 15.36 4 256 x 24k, 384 x 16k 10 12.288 6 256 x 16k n=25 m=128 122.88m p=5 24.576m 12 256 x 8k
rock2 data sheet v1.1 08/04/06 rockchip electronics 43 of 128 n=8, m=64: 24mhz/ 8 x64=192mhz fvco/(p*q) = i2smclk , t=mclk _div+1, p*q= i2smclk_div+1 (pll ? 1mhz <= osc/n <= 15mhz; 100mhz <= fvco <= 500mhz) ? n m t p*q ??????? n_div = n ? 2 m_div = m ? 2 mclk_div = t ? 1 i2smclk_div = p*q ? 1 4 96 6 64 8 48 12 32 16 24 n=8 m=128 384mhz 32 12 32 12mhz 12mhz fvco t mclk(dsp) [mhz] p*q i2smclk (use pll) i2smclk (use osc/2) 2 96 4 48 6 32 8 24 12 16 n=8 m=64 192mhz 16 12 16 12mhz 12mhz 1 96 2 48 4 24 6 16 n=8 m=32 96mhz (initial) 8 12 8 12mhz 12mhz 1 100 2 50 4 25 6 16.66 n=12 m=50 100mhz 8 12.5 8 - 12mhz osc 2 100 4 50 6 33.33 8 25 n=12 m=100 200mhz 10 20 8 - 12mhz osc
rock2 data sheet v1.1 08/04/06 rockchip electronics 44 of 128 3.7.6 register descriptions register address r/w description reset value mclkcon 0x0001_ee00 r/w main clock control register 0x 0001 i2smclkcon 0x0001_ee04 r/w i2s clock control register 0x 0107 ahbclkcon 0x0001_ee08 r/w ahb clock control register 0x 0000 apbclkcon 0x0001_ee0c r/w apb clock control register 0x 0000 pll_ndiv 0x0001_ee10 r/w pll 5-bit divider count register 0x 0006 pll_mdiv 0x0001_ee14 r/w pll 9-bit feedback divider count register 0x 001e pll_oddiv 0x0001_ee18 r/w pll output divider count register 0x 0000 pll_pdbp 0x0001_ee1c r/w pll output control register 0x 0001 pwrcon 0x0001_ee38 r/w clock power control register 0x 001f main clock control register (mclkcon) mclkcon bit description initial state reserved [15:8] reserved - mclk_div [7:0] 8-bit prescaler value the input clock is pll clk_out mclk = input clock / (mclk_div + 1) 0000,0001b i2s main clock control register (i2smclkcon) i2smclkcon bit description initial state reserved [15:8] reserved - i2smclk_sel [8] 0: select i2smclk_div clock 1: select 12mhz 1 i2smclk_div [7:0] 8-bit prescaler value the input clock is pll clk_out i2smclk = clk_out / (i2smclk_div + 1) 0000,0111b
rock2 data sheet v1.1 08/04/06 rockchip electronics 45 of 128 ahb clock control register (ahbclkcon) ahbclkcon bit description initial state reserved [15:2] reserved - ahbclk_div [1:0] ahb clock output divider count register the input clock is mclk 00: mclk 01: mclk/2 10: mclk/4 11: mclk/8 00b apb clock control register (apbclkcon) apbclkcon bit description initial state reserved [15:2] reserved - apbclk_div [1:0] apb clock output divider count register the input clock is hclk 00: hclk 01: hclk /2 10: hclk /4 11: hclk /8 00b pll input divider register (pll_ndiv) pll_ndiv bit description initial state reserved [15:5] reserved - pll_ndiv [4:0] pll 5-bit input divider count register, this signal must connect to pll n = pll_ndiv + 2 0,0110b pll input divider register (pll_mdiv) pll_mdiv bit description initial state reserved [15:9] reserved - pll_mdiv [8:0] pll 9-bit feedback divider count register, this signal must connect to pll m = pll_mdiv + 2 0,0001,1110b
rock2 data sheet v1.1 08/04/06 rockchip electronics 46 of 128 pll feedback divider register (pll_oddiv) pll_oddiv bit description initial state reserved [15:2] reserved - pll_oddiv [1:0] pll output divider count register, this signal must connect to pll 00: 1/1 01: 1/2 10: 1/2 11: 1/4 00b pll output enable register (pll_pdbp) pll_pdbp bit description initial state ? [15:2] reserved - pll_pd [1] 1= pll power down; 0= pll is power on this signal must connect to pll 0 pll_bp [0] 1= pll bypass; 0= use pll output this signal must connect to pll 1 clock power control register (pwrcon) pwrcon bit description initial state ? [15:5] reserved - dmaclk_en [4] 0 = disable 1 = enable 1 memctrlclk_en [3] 0 = disable 1 = enable 1 sdclk_en [2] 0 = disable 1 = enable 1 i2sclk_en [1] 0 = disable 1 = enable 1 usbclk_en [0] 0 = disable 1 = enable 1
rock2 data sheet v1.1 08/04/06 rockchip electronics 47 of 128 3.7.7 example software !---------------pll: 140mhz----70mhz-------------------- mov r0, clock_mclkcon ! mclk= clkout/4 mov r2, 0x03 st r2, r0 call delay_20nop mov r0, clock_pll_pdbp ! bp=1; clkout=24mhz mov r2, 0x01 ! mclk=hclk=pclk=24/4=6mhz st r2, r0 call delay_100nop mov r0, clock_ahbclkcon ! hclk=mclk mov r2, 0x00 st r2, r0 call delay_20nop mov r0, clock_apbclkcon ! pclk=hclk mov r2, 0x00 st r2, r0 call delay_20nop mov r0, clock_pll_ndiv ! pll_ndiv=10+2=12 mov r2, 10 st r2, r0 call delay_20nop mov r0, clock_pll_mdiv ! pll_mdiv=68+2=70 mov r2, 68 ! pllclk=24mhz =70/12*24=140mhz st r2, r0 call delay_500us mov r0, clock_pll_pdbp ! bp=0, clkout= pllclk=140mhz mov r2, 0x00 ! mclk=hclk=pclk=140/4=35mhz st r2, r0 call delay_20nop mov r0, clock_apbclkcon ! pclk=hclk/4, from 0 ? 4 ? 2 mov r2, 0x02 st r2, r0 call delay_20nop mov r0, clock_apbclkcon ! pclk=hclk/2=17.5mhz mov r2, 0x01 st r2, r0 call delay_20nop mov r0, clock_mclkcon ! mclk=140/2=70mhz, hclk=70mhz, pclk=hclk/2=35mhz mov r2, 0x01 st r2, r0 call delay_20nop mov r0, clock_ahbclkcon ! hclk=mclk/4 mov r2, 0x02
rock2 data sheet v1.1 08/04/06 rockchip electronics 48 of 128 st r2, r0 mov r0, clock_ahbclkcon ! mclk=70mhz, hclk=mclk/2=35mhz, pclk=hclk/2=17.5mhz mov r2, 0x01 st r2, r0 call delay_20nop mov r0, clock_apbclkcon ! mclk=70mhz, pclk=hclk=mclk/2=35mhz mov r2, 0x00 st r2, r0 call delay_20nop ???.. !---------------pll: 100mhz----50mhz-------------------- mov r0, clock_mclkcon ! mclk= clkout/4 mov r2, 0x03 st r2, r0 call delay_20nop mov r0, clock_pll_pdbp ! bp=1; clkout=24mhz mov r2, 0x01 ! mclk=24/4=6mhz, pclk=hclk=mclk/2=3mhz st r2, r0 call delay_20nop mov r0, clock_pll_mdiv ! pll_mdiv=48+2=50 mov r2, 48 ! pllclk =50/12*24=100mhz st r2, r0 call delay_500us mov r0, clock_pll_pdbp ! bp=0, clkout= pllclk=100mhz mov r2, 0x00 ! mclk= 100/4=25mhz, hclk=pclk= mclk/2=12.5mhz st r2, r0 call delay_20nop mov r0, clock_mclkcon ! mclk=100/2=50mhz, hclk=pclk= mclk/2=25mhz mov r2, 0x01 st r2, r0 call delay_20nop ? 1 mclk hclk pclk ?????? 4 ??? 2 ?? pll ???? bypass ? bp=1 ? pll ?? 0.5 pll ? bp=0
rock2 data sheet v1.1 08/04/06 rockchip electronics 49 of 128 3.8 pwm 3.8.1 overview rock2 has an internal timer a. it supported mode of pwm (pulse width modulation) . the timer has internally one pre-scale regist er (ta_pre), one counter register (ta_cnt), and two data registers (ta_data0, ta_data1). the ta_cnt is incremented by count clock that is pre-scaled by ta_pre value from pc lk. the role of ta_data0 and ta_data1 is different. function list: ? 16-bits timer ? support pwm mode ? 0 ~ 100 % duty ratio pwm signal generation clock requirement: re-scaling the counting clock ( pclk) with the 10-bits pre-scale register (ta_pre) count_clk = pclk / (ta_pre+1) 3.8.2 block diagram
rock2 data sheet v1.1 08/04/06 rockchip electronics 50 of 128 3.8.3 block i/os pwm i/o description register files interface ta_clr i clear operation ta_en i timer enable ta_data0(15:0) i timer data0 ta_data1(15:0) i timer data1 tacnt(15:0) o timer counter apb slave interface i/os total: application interface count_clk i counter clock resetn i an active-low, asynchronous reset. mat_int0 o timer match data0 interrupt mat_int1 o timer match data1 interrupt ta_out o pwm output
rock2 data sheet v1.1 08/04/06 rockchip electronics 51 of 128 pwm mode the ta_cnt value is compared to the two buffers that are updated with the values of ta_data0 and ta_data1 register. when (ta_cnt) is equal to the buffer of ta_data0, ta_mat_int0 interrupt occurs and the timer continues the counting operation without clearing the counter. when (ta_cnt) is equal to the buffer of ta_data1, the timer generates ta_mat_int1 interrupt, clears the ta_cnt register, and updates the internal buffers with the values of ta_data0 register and ta_data1 register. for each interrupt, the ta_out is toggled. as the values of ta_data0 and ta_data1 register are updated after the ta_mat_int1 interrupt, the new values in ta_data0 and ta_data1 registers have an effect after ta_mat_int1 occurs. this mode is used to generate a configurable pwm signal. the clock period of pwm signal can be set in ta_data1 register and the duty ratio can be set in ta_data0 register. the operation of this mode is described in the figure 5. the pulse is low/(low+high)==(ta_data0+1)/(ta_data1+1) ex: ta_data0:ta_data1=5:5=1 ? when 5 adc_clk, ta_out will always high; ta_data0:ta_data1=5:3>1 ? ta_out will always low; ta_data0:ta_data1=5:7=1 ? ta_out 6 clocks low, 2 clocks high; figure 5. pwm mode operation int_tx 200 75 150 200 200 100 100 50 0 ta_cnt value ta_out ta_data1=201 ta_data1=201 ta_data1=201 ta_data1=101 ta_data1=200 ta_data0=150 start (period=200) ta_data0=100 ta_data0=75 ta_data0=50 ta_data1=100(period change) write write write depending on the values of the ta_data0 and ta_data1, the shapes of the pwm signals are different. the detailed waveforms in pwm m ode are shown in figure 6, figure 7, figure 8, and figure 9.
rock2 data sheet v1.1 08/04/06 rockchip electronics 52 of 128 figure 6. pwm mode when ta_data0 = 1 and ta_data1=2 count_clk tm_en tm_clr data0_buf data1_buf 0002 0001 0000 0001 ta_cnt 0002 0000 ta_int0 ta_int1 ta_out initially ta_data0 = 1 and ta_data1=2 0001 0002
rock2 data sheet v1.1 08/04/06 rockchip electronics 53 of 128
rock2 data sheet v1.1 08/04/06 rockchip electronics 54 of 128 3.8.4 register descriptions name width address(virtual) r/w description reset timer registers tacon 16 0x0001_ec80 r/w control register 0x0000 tacmd 16 0x0001_ec84 r/w command register 0x0000 tadata0 16 0x0001_ec88 r/w data0 register 0x0000 tadata1 16 0x0001_ec8c r/w data1 register 0x0000 tapre 16 0x0001_ec90 r/w prescale register 0x0000 tacnt 16 0x0001_ec94 r counter register 0x0000 tacon bits name type description 31-3 reserved 2 ta_out r the pwm output 1 ta_int1 r match interrupt 1 status. th is field is updated when a match interrupt 1 occurs. 0 ta_int0 r match interrupt 0 status. th is field is updated when a match interrupt 0 occurs. tacmd bits name type description 31-2 reserved 1 ta_clr w clear operation. this field is always zero when read. 0 = nothing occurs 1 = initialize the timer. - clear the counter register. - ta_data0 and ta_data1 are updated to the internal buffers 0 ta_en r/w timer enable command 0 = disable the timer 1 = enable the timer
rock2 data sheet v1.1 08/04/06 rockchip electronics 55 of 128 tadata0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_data0 bits name type description 15:0 ta_data0 r/w the target counting value is stored in this field. when the counter value equals to this register, a mat_int0 interrupt is generated. this field is updated to the internal data buffer 0 when mat_int0 occurs or when clear operation is executed. tadata1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_data1 bits name type description 15:0 ta_data1 r/w the target counting value is stored in this field. when the counter value equals to this register, a mat_int1interrupt is generated. this field is updated to the internal data buffer 1.when mat_int1occurs or when clear operation is executed. tapre 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_pre bits name type description 9:0 ta_pre r/w pre-scale value (it is include in the clock module) count_clk = pclk / (ta_pre+1) tacnt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_cnt bits name type description 15:0 ta_cnt r counter register
rock2 data sheet v1.1 08/04/06 rockchip electronics 56 of 128 3.8.5 example software mov r0, pwm_tacmd mov r2, 0x00 !disable st r2, r0 mov r0, pwm_tapre mov r2, 32 st r2, r0 mov r0, pwm_tadata0 !2/3 int: 33*300=9900clks mov r2, 199 st r2, r0 mov r0, pwm_tadata1 mov r2, 299 st r2, r0 call delay_100nop mov r0, pwm_tacmd mov r2, 0x03 !enable and clr st r2, r0 bits %imask, 4 !enable pwm interrupt mov r0, gpio_pcon2b !pwm out to p2.13,14,15 mov r2, 0xfd55 mov r3, 0x0 stdu r2, r0, 2 ??.. mov r0, gpio_pcon2b !pwm out to p2.14,15 mov r2, 0xf555 mov r3, 0x0 stdu r2, r0, 2 ??.. mov r0, gpio_pcon2b !pwm out to p2.15 mov r2, 0xd555 mov r3, 0x0 stdu r2, r0, 2 ??..
rock2 data sheet v1.1 08/04/06 rockchip electronics 57 of 128 3.9 10bit adc 3.9.1 overview the 10-bit a/d converter (adc) module is used to convert the analog signal into the digital signal. adc is generate by pclk by setting the adcfre register. the adc_clk can be prescale to be pclk/1, pclk/2, pclk/3?.pclk/128. 3.9.2 interface figure 3. adc controller timing characteristics adc_clk 12 14 adc_soc adc_eoc adc_ready adcdat0 b[9:0]_n b[9:0]_n-1 reset adc_pd power down 3.9.3 block i/os adc controller i/o description register file interface pd i a/d converter power down mode soc i a/d converter start sel(2:0) i a/d converter input select eoc i end of conversion b(9:0) i a/d converted data adc_ready o adc ready (high), when low, adc is busy adc_rstn i reset signal, low active
rock2 data sheet v1.1 08/04/06 rockchip electronics 58 of 128 register file interface i/os total: application interface ain[3:0] i 4 channel analog input rext100k i external 100k reference resistor vref i external reference voltage adc_clk i a/d converter clock adc_rst o reset signal, reset=1,the chip is reset pclk i apb clock 3.9.4 register descriptions adc controller internal registers register address r/w description reset value adccon 0x0001_ed00 r/w adc control register 0x0004 adcdat0 0x0001_ed04 r adc conversion data - adcfre 0x0001_ed08 r/w adc frequency control register 0x0000 adcrdy 0x0001_ed0c r adc ready signal register 0x0000 adc control (adccon) register adccon bit r/w description initial state [15:5] nc sel_mux [4:2] r/w analog input channel select. 000 = ain0 001 = ain1 010 = ain2 011 = ain3 100 = ain4 [vbg] 000b adc_pd [1] r/w power down mode select. 0 = normal operation mode 1 = power down mode 0 adc_soc [0] r/w a/d conversion starts by setting this bit. 0 = no operation 1 = a/d conversion starts and this bit is cleared after 2 adc_clk after the start-up. 0
rock2 data sheet v1.1 08/04/06 rockchip electronics 59 of 128 adc conversion data (adcdat0) register adcdat0 bit r/w description initial state b[9:0] [9:0] r normal adc conversion data value. (0 ~ 3ff) ? adc frequency pre-scale control (adcfre) register adcfre bit r/w description initial state [15-8] - nc adc_sel [7:0] r/w adc frequency scale as: 000 = pclk/1 adc_clk==pclk/(adc_sel+1) 00 adc ready control (adcrdy) register adcrdy bit r/w description initial state [15:1] nc adc_ready [0] r/w adc is in ready(read only) 0 = not ready 1 = ready, the data output is in adcdat0 1 3.9.5 example software mov r0, adc_adcfre ! set adc_clk to ~1mhz, pclk/10 mov r2, 0x9 st r2, r0 mov r0, adc_adccon ! [4:2]: sel ch, [1]: pd, [0]: soc mov r2,0b00001 ! sel adc0 st r2, r0 ?..delay some clks?. mov r0, adc_adcrdy ld r2, r0 ! ==1? ! if ==1, then mov r0, adc_adcdat0 ! read adc0 data to r2 ld r2, r0
rock2 data sheet v1.1 08/04/06 rockchip electronics 60 of 128 3.10 i2dsp master/slave 3.10.1 overview the audio interface adopt i2dsp mode to transmits pcm audio data to external dac and receives pcm audio data from external adc. to minimize the number of pins required and to keep wiring simple, a 3-line serial bus which consists of a data line for time-multiplexed two- channel data(left/right), a word select line and a clock line is used. in rock2, the i2dsp mode audio interface bus has 2 data lines(one for reception and 1 for transmission), 2 word select lines (lrck) , and 1 mclk line (i2dsp_mclk). the i2dsp mode audio interface bus has two modes for data transfer. in transmission mode, i2dsp module makes a request for pcm audio data to dma module and dma module brings audio data from sram. in reception mode, i2dsp module gets audio data from external source and stores them into sram by requesting to dma . 1 data lines are synchronized with 1 word select line and 1 clock line for transmission mode and 1 data line is synchronized with 1 word select line and 1 clock line for reception mode. in i2dsp mode, the chip which generates the bit clock is called master. either transmitter or receiver of audio data has to generate the bit cl ock and word select clock as a master since they use the same clock signal for data transfer. when rock2 acts as a slave in i2dsp mode, it receives two clock signals (bit clock and word select clock) from a master even when it transfers audio data. when rock2 acts as a master in i2dsp mode, it generate two clock signals (bit clock and word select clock) to the codec. function list: ? 2 data transfer modes ? transmission, reception ? dma mode transfer, dsp interrupt/inquiry mode. ? 8 x 24-bit buffer for transmission and 8 x 24-bit buffer for reception
rock2 data sheet v1.1 08/04/06 rockchip electronics 61 of 128 ? 16/18/20/24 bit data per channel ? 1 channel for transmission and 1 channel for reception ? msb-first transfer mode only ? i2dsp master and slave mode ? 12m master clock output only ? 250,272/273fs(sampling frequency) serial bit clock per frame ( left channel + right channel ) ? 250,272/273fs master clock(dac clock) clock requirement: audio main clock (i2dspmclk) is 12m only. the sampling frequency of audio data come from external codec. the relationship between sampling frequency (fs) and audio main clock is shown in table 1. serial bit clock (sck) is equal to mclk, data bit per channel(table 2) is set by the value of configuration register(i2dsp_txconf, i2dsp_rxconf). word select signal (lrck) has the same frequency as sampling frequency(fs). table 1. sample rate look-up table for master mode table 1. the frequency of sample rate of master mode mclk is 12m only lrck (fs) 8 khz 11.025 khz 16 khz 22.05 khz 32 khz 44.10 khz 48 khz fs 250*6 272*4 250*3 272*2 250*3/2 272 250 table 2. sample rate look-up table for slave mode table 2. the frequency of sample rate of slave mode mclk is 12m only, and lrck is generate from codec lrck (fs) 8 khz 11.025 khz 16 khz 22.05 khz 32 khz 44.10 khz 48khz fs 250*6 272/273*4 250*3 272/273*2 250*3/2 272/273 250
rock2 data sheet v1.1 08/04/06 rockchip electronics 62 of 128 3.10.2 block diagram apb slave i/f (w) write buffer 8 fifo transmiter sdo word select receiver sdi read buffer 8 fifo apb slave i/f (r) pclk domain i2smclk domain figure 2. block diagram lrck_dac int_tx int_rx resetn w_sel i2smclk 24 24 i2dspmclk sck lrck_adc 3.10.3 block i/os apb slave interface pclk i apb clock. presetn i an active-low, asynchronous apb interface domain reset. psel i apb peripheral select. paddr(9:0) i apb address bus. pwdata(31:0) i apb write data bus. pwrite i apb write control. penable i apb enable control that indicates the second cycle of the apb frame. prdata(31:0) o apb readback data. apb slave interface i/os total: application interface sck i i2dsp mode sereial data clock lrck o i2dsp mode word select. sdo o i2dsp mode serial data output i2smclk i i2dsp module main clock input sdi i i2dsp mode serial data input i2 dsp mclk o i2dsp mode main clock output to external codec i2c_ext o select external i2dsp_ext,i2c_ext interface resetn i i2dsp slave asynchronous reset. active low sw_codec_ rstn o codec asynchronous reset. active low
rock2 data sheet v1.1 08/04/06 rockchip electronics 63 of 128 3.10.4 interface figure 3. i2dsp mode transmit interface msb (1st) (2nd) lsb msb (1st) (2nd) lsb 0 i2dsp _clk lrck_dac sdo msb (1st) (2nd) 1 sck 1/fs left right input word length figure 3 . dsp mode write timing figure 4. i2dsp mode receive interface msb (1st) (2nd) lsb msb (1st) (2nd) lsb 0 i2dsp _clk lrck_adc sdi msb (1st) (2nd) 1 sck 1/fs left right input word length figure 4 . dsp mode read timing in rock2, the i2dsp mode audio interface modul e is applicable to dsp interface format as shown above. i2dsp-bus format starts data transfer at the next sck clock after word select signal (lrck) rising edge. i2dsp-bus format transfer the left channel and right channel data continuously, and msb of audio data are transferred firs t. if there exists more serial clock bits in one frame than serial data bits, the remaining clock bits are stuffed with zero's in each case.
rock2 data sheet v1.1 08/04/06 rockchip electronics 64 of 128 start and stop condition to make i2dsp module active, i2s_clk_en bit in i2sclkcon must be set to ?1?. after i2dsp module becomes active, setting command register (i2dsptxcom or i2dsprxcom) to ?0x0000 000e? drives i2dsp to its function mode. i2s_clk_en bit in command register decides the generation of main clock(mclk) and makes i2dsp bus stop immediately after it is set to ?0?. to make i2dsp inactive, the procedure is as follows. set i2s_clk_en to '0'. fifo model: (using dma) the transmit and receive block all have 8words (24bytes) fifo. when transmit, dma first check signal i2dsp_tx_vilid, which is a request signal, if it is high, then transmit data to txfifo0-7. if the txfi fos are not full, i2dsp_tx_nfull is high, it transmit i2dsp_tx_vilid to dma. if the txfifos are full, i2dsp_tx_nfull is low, it resets i2dsp_tx_vilid to low, dma is waiting a hi gh of i2dsp_tx_vilid for next transmition. as the shift register reads a data from txfifos, i2dsp_tx_nfull comes high. and then the i2dsp_tx_vilid comes high as a request to dma. when receive, the shift register puts data to the rxfifos, i2dsp_rx_nempty will be set to high, then transmit a i2dsp_rx_vilid to dma, if dma reads all the data, i2dsp will reset i2dsp_rx_nempty to low, and i2dsp_rx_vilid will be low. when the rxfifos are full, the i2dsp_rx_full will be high, waiting for the dma to read the data. note: i2dsp_tx_vilid is same as i2dsp_tx_nfull, but when dma_ack is from low to high, i2dsp_tx_vilid will be low first, if i2dsp_tx_nfull is still high level, i2dsp_tx_vilid will be high at next pclk. i2dsp_rx_vilid is same as i2dsp_rx_nempty, but when dma_ack is from low to high, i2dsp_rx_vilid will be low first, if i2dsp_rx_nempty is still high level, i2dsp_rx_vilid will be high at next pclk.
rock2 data sheet v1.1 08/04/06 rockchip electronics 65 of 128 fifo model: (using dsp) when transmit, dsp first check signal i2dsp_tx_nfull, if it is high, then transmit data to txfifo0-7. if the txfifos are full, it pulls i2dsp_tx_nfull to low, dsp waiting a high of i2dsp_tx_nfull for next transmition. as the shift register reads a data from txfifos, i2dsp_tx_nfull comes high. when receive, the shift register puts data to the rxfifos, dsp first check signal i2dsp_rx_nempty, if it is high, then reads data from rxfifos. if it reads all the data, i2dsp will reset i2dsp_rx_nempty to low. when the rxfifos are full, the i2dsp_rx_full will be high i2dsp_rx_vilid i2dsp_rx_nempty i2dsp_tx_vilid i2dsp_tx_nfull
rock2 data sheet v1.1 08/04/06 rockchip electronics 66 of 128 3.10.5 register descriptions name width address r/w description reset value i2dsp_txconf 16 0x0001_ec00 r/w tx configuration register 0x0000 i2dsp_txcom 16 0x0001_ec08 r/w tx command register 0x0000 i2dsp_txdb 32 0x0001_ec10 w tx data buffer 0x0000 0000 i2dsp_dpctrl 16 0x0001_ec20 r/w data pointer control 0x0000 i2dsp_rxconf 16 0x0001_ec30 r/w rx configuration register 0x0000 i2dsp_rxcom 16 0x0001_ec34 r/w rx command register 0x0000 i2dsp_status 16 0x0001_ec38 r status register 0x0000 i2dsp_rxdb 32 0x0001_ec40 r rx data buffer 0x0000 0000 i2c_ext 16 0x0001_ec60 r/w i2c external 0x0000 sw_codec_rstn 16 0x0001_ec64 r/w codec rstn 0x0000 i2dsp tx configuration register (i2dsp_txconf) i2dsp_txconf bit description initial state [15:6] reserved 0 transmit dac fs control [5:3] 0 : 48k 1 : 44.1k 2 : 32k 3 : 22.05k 4 : 16k 5 : 11.025k 6 : 8k 7 : 8k 000b master/slave mode select [2] 0: slave mode 1: master mode 0 serial data bit per channel [1:0] 00 = 16 bit 10 =20 bit 01 = 18 bit 11 = 24 bit 00b
rock2 data sheet v1.1 08/04/06 rockchip electronics 67 of 128 i2dsp tx command register (i2dsp_txcom) i2dsp_txcom bit description initial state [15:3] reserved 0 i2dsp interface enable [2] 0 = i2dsp interface disable (stop) 1 = i2dsp interface enable (start) 0 tx enable select [1] 0 = no transfer 1 = transmit mode on 0 dma service request enable [0] 0 = dma request disable 1 = dma request enable 0 i2dsp data buffer register (i2dsp_txdb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msb(16/20/18/24) data lsb16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb18 lsb20 lsb24 x i2dsp_txdb bit description initial state i2dsp transmit data [31:8] 24 bits transmit data to dac 0 [7:0] reserved 0 i2dsp rx configuration register (i2dsp_rxconf) i2dsp_rxconf bit description initial state [15:6] reserved 0 receive adc fs control [5:3] 0 : 48k 1 : 44.1k 2 : 32k 3 : 22.05k 4 : 16k 5 : 11.025k 6 : 8k 7 : 8k 000b master/slave mode select [2] 0: slave mode 1: master mode 0 serial data bit per channel [1:0] 00 = 16 bit 10 = 20 bit 01 = 18 bit 11 = 24 bit 00b
rock2 data sheet v1.1 08/04/06 rockchip electronics 68 of 128 i2dsp rx command register (i2dsp_rxcom) i2dsp_rxcom bit description initial state [15:3] reserved 0 rx enable select [1] 0 = no receive 1 = receive mode on 0 dma service request enable [0] 0 = dma request disable 1 = dma request enable 0 i2dsp rx data buffer register (i2dsp_rxdb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msb(16/20/18/24) data lsb16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb18 lsb20 lsb24 x i2dsp_rxdb bit description initial state i2dsp receive data [31:8] 24 bits receive data from adc 0 [7:0] reserved 0 i2dsp status register (i2dsp_status) i2dsp_status bit description initial state [15:2] reserved 0 rx_fifo_nemp [1] rx data buffer state flag 1 = not empty 0 = empty 0 tx_fifo_nful [0] tx data buffer state flag 1 = not full 0 = full 1
rock2 data sheet v1.1 08/04/06 rockchip electronics 69 of 128 i2dsp data pointer control (i2dsp_dpctrl) register name bit description initial state reserved [15:2] 0 rx_fiforst [1] reset the receive fifo. 0 = no effect 1 = reset the receive fifo 0 tx_fiforst [0] reset the transmit fifo. 0 = no effect 1 = reset the transmit fifo 0 i2c external control (i2c_ext) register name bit description initial state reserved [15:2] 0 i2dsp_ext [1] set i2dsp to external . 0 = to internal codec 1 = to external i2dsp pad. 0 i2c_ext [0] set i2c to external . 0 = to internal codec 1 = to external i2c pad. 0 codec reset (sw_codec_rstn) register name bit description initial state reserved [15:1] 0 sw_codec_rstn [0] set codec to reset, low active. 0 = to internal codec reset 1 = codec reset deactive 0 note: when the external resetn is low, the sw_codec_rstn will be reset to 0, until the external resetn goes high, dsp will run the software and then set sw_codec_rstn to high to enable codec. when using codec, you can set sw_codec_rstn to low and then high to reset the codec.
rock2 data sheet v1.1 08/04/06 rockchip electronics 70 of 128 3.10.6 example software !--------- transmit dac & adc ----------- ! txconf = 32'b00_0011; // [5:3]: fs, [2]:master, [1:0]:24-16bits ! txcom = 32'b110; // [2]: i2dsp_en, [1]: tx_en, [0]: nc ! dpctrl = 32'b11; // [1]: rxfiforst, [0]: txfiforst ! rxconf = 32'b00_0011; // [5:3]: fs, [2]: master, [1:0]: 24-16bits //slave ! rxcom = 32'b10; //[1]: rx_en, [0]: nc ! mov r0, i2dsp_txconf ! tx slave; [5:3]: fs=48khz, [2]:slave mode, [1:0]: 20bits mov r2, 0b000010 st r2,r0 mov r0,i2dsp_txcom ! i2dsp_en, tx enable mov r2,0b110 st r2,r0 mov r0, i2dsp_dpctrl ! rxfiforst, txfiforst mov r2, 0b11 st r2, r0 mov r0, i2dsp_rxconf ! rx ; [5:3]: fs=48khz, [2]: master,[1:0]: 24bits mov r2, 0b000011 st r2, r0 mov r0, i2dsp_rxcom ! rx enable mov r2, 0b10 st r2, r0 //----- read data from table, then write to i2dsp ----- lda r5, data_table ! read from table mov %loop0, 40 ! data length write_i2dsp_loop: mov %loop1, 0x200 write_i2dsp_loop1: mov r0, i2dsp_status ! read status of tx_fifo_nfull ld r6, r0 mov r4, 0x1 and r6, r4 cmp r6, r4 bz write_i2dsp_1 ! tx fifo is not full, send next one agn1 write_i2dsp_loop1 write_i2dsp_1: bits %smode,5 !!!!table!!!! lddu r2, r5, 2 bitc %smode,5 mov r0,i2dsp_txdb stdu r2, r0, 2 ! r3[15:0], r2[15:8]: 24bits agn0 write_i2dsp_loop
rock2 data sheet v1.1 08/04/06 rockchip electronics 71 of 128 //---read data from i2dsp --- bits %smode,0 mov %loop0, 40 ! data length read_i2dsp_loop: mov %loop1, 0x200 read_i2dsp_loop1: mov r0, i2dsp_status ld r6, r0 mov r4, 0x2 and r6, r4 cmp r6, r4 bz read_i2dsp_1 ! rx fifo is not empty, read next one agn1 read_i2dsp_loop1 read_i2dsp_1: mov r0, i2dsp_rxdb+1 ! read only high 16bits ld r6, r0 ??.. store r6 agn0 read_i2dsp_loop
rock2 data sheet v1.1 08/04/06 rockchip electronics 72 of 128 3.11 i2c 3.11.1 overview the i2c bus is a two-wire serial interface. the dw _apb_i2c module can operate in both standard mode (with data rates up to 100 kb/s), fast mode (with data rates up to 400 kb/s). the i 2 c serial clock determines the transfer rate. the i 2 c interface protocol is setup with a master and slave. the master is responsible for generating the clock and controlling the transfer of data. the slave is responsible for either transmitting or receiving data to/from the master. the acknowledgement of data is sent by the device that is receiving data, which can be either the master or the slave. the prot ocol also allows multiple masters to reside on the i 2 c bus, which requires the masters to arbitrate for ownership. the slaves each have a unique address that is determined by the system designer. when the master wants to communicate with a slave, the master transmits a start condition that is then followed by the slave?s address and a control bit (r/w) to determine if the master wants to transmit data or receive data from the slave. the slave then sends an acknowledge (ack) pulse after the address and r/w bit is received to notify the master that the slave has received the request. if the master (master-transmitter) is writing to the slave (slave-receiver), the re ceiver receives a byte of data. this transaction continues until the master term inates the transmission with a stop condition. if the master is reading from a slave, the slave transmits a byte of data to the master, and the master then acknowledges the transaction with the ack pulse. this transaction continues until the master terminates the transmission by not acknowledging th e transaction after the last byte is received, and then the master issues a stop condition or addresses another slave after issuing a restart condition. this is illustrated in figure 3 . figure 3: dw_apb_i2c start and stop condition the dw_apb_i2c is a synchronous seri al interface. the data signal (sda ) is a bidirectional signal and changes only while the serial clock signal (scl) is low. the output drivers are open-drain or open-collector to perform wire-and functions on the bus. the maximum number of devices on the bus is limited by only the maximum capacitance specific ation of 400 pf. data is transmitted in byte packages.
rock2 data sheet v1.1 08/04/06 rockchip electronics 73 of 128 addressing slave protocol there are two address formats: the 7-bit address format and the 10-bit address format. during the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the lsb bit (bit 0) is the r/w bit as shown in figure 5 . when bit 8 is set to 0, the master writes to the slave. when bit 8 (r/w) is set to 1, the master read s from the slave. data is transmitte d most significant bit (msb) first. during 10-bit addressing, two bytes are transferred to set the 10-bit address. the transfer of the first byte contains the following bit definition. the first five bits (bits 7:3) notify the slaves that this is a 10-bit transfer followed by the next two bits (bits 2:1), which set the slaves address bits 9:8, and the lsb bit (bit 8) is the r/w bit. the second byte transferred sets bits 7:0 of the slave address. figure 6 shows the 10-bit address format, and table 3 on page 31 defines the special purpose and reserved first byte addresses. figure 5: 7-bit address format transmitting and receiving protocol all data is transmitted in byte format, with no limi t on the number of bytes tran sferred per data transfer. after the master sends the address and r/w bit or the master transmits a byte of data to the slave, the slave-receiver must respond with the acknowledge signal. when a slave-receiver does not respond with an acknowledge pulse, the master aborts the transfer by issuing a stop condition. the slave shall leave the sda line high so the master can abort the transfer. if the master-transmitter is transmitting data as shown in figure 7 on page 32 , then the slave-receiver responds to the master-transmitter with an acknowledge pulse after every byte of data is received.
rock2 data sheet v1.1 08/04/06 rockchip electronics 74 of 128 figure 7: master-transmitter protocol if the master is receiving data as shown in figure 8 , then the master responds to the slave-transmitter with an acknowledge pulse after a byte of data has been received, except for the last byte. this is the way the master-receiver notifies the slave-transmitter that this is th e last byte. the slave-transmitter relinquishes the sda line after detecting the no acknowledge so that the master can issue a stop condition.
rock2 data sheet v1.1 08/04/06 rockchip electronics 75 of 128 figure 8: master-receiver protocol when a master does not want to relinquish the bus with a stop condition, the master can issue a repeated start condition. this is identical to a start condition except it occurs after the ack pulse. the master can then communicate with the same slave or a different slave. start byte transfer protocol the start byte transfer protocol is set up for systems that do not have an on board dedicated i 2 c hardware module. when the dw_apb_i2c is addressed as a slave, it always samples the i 2 c bus at the highest speed supported so that it never requires a start byte transfer. however, when the dw_apb_i2c is a master, it supports the generation of start byte transfers at the beginning of every transfer in case a slave device requires it. the start byte protocol consists of seven zeros being transmitted followed by a 1, as illustrated in figure 9. this allows the processor that is polling the bus to under-sample the address phase until 0 is detected. once the microcontroller detects a 0, it switches from the under sampling rate to the correct rate of the master. the start byte procedure is as follows: 1. master generates a start condition. 2. master transmits the start byte (0000 0001). 3. master transmits the ack clock pulse. 4. no slave sets the ack signal to 0. 5. master generates a repeated start (sr) condition figure 9: start byte transfer a hardware receiver does not respond to the start byte because it is a reserved address and resets after the sr (restart condition) is generated. master mode operation initial configuration to use the dw_apb_i2c as a master, perform the following steps: 1. disable the dw_apb_i2c by writing 0 to the ic_enable register. 2. write to the ic_sar register to set the slave address, which is the address to which the dw_apb_i2c responds. 3. write to the ic_con register to set the maximum speed mode supported for slave operation and the desired speed of the dw_apb_i2c master-initiated transfers, either 7-bit or 10-bit addressing. 4. write to the ic_tar register to the address of the i 2 c device to be addressed. it also indicates whether adding a start byte or issuing a general call is going to occur. 5. only applicable for high-speed mode transfers . write to the ic_hs_maddr register the desired
rock2 data sheet v1.1 08/04/06 rockchip electronics 76 of 128 master code for the dw_apb_i2c. 6. enable the dw_apb_i2c with the ic_enable register. 7. commands and data to be sent may be written now to the ic_data_cmd register. if the ic_data_cmd register is written before the dw_apb_i2c is enabled, the data and commands are lost as the buffers are kept cleared when dw_apb_i2c is not enabled. master transmit and master receive the dw_apb_i2c supports switching back and forth between reading and writing dynamically. to transmit data, write the data to be written to the lower byte of the ic_data_cmd register. the cmd bit, bit 8, should be written to 0 for write operations. subsequently, a read command may be issued by writing ?don?t cares? to the lower byte of the ic_ data_cmd register, and a 1 should be written to the cmd bit. as data is transmitted and received, the transmit and receive buffer status bits and interrupts change. 3.11.2 register ic_con i 2 c control register 0 bits name r/w description 15:7 reserved n/a reserved. 6 ic_slave_disable r/w this bit controls whether i 2 c has its slave disabled after reset. the slave can be disabled by programming a ?1? into ic_con[6]. by default the slave is enabled. 0: slave is enabled 1: slave is disabled reset: ic_slave_disable 5 ic_restart_en r/w determines whether restart conditions may be sent when acting as a master. some older slaves do not support handling restart conditions. restart conditions are used in several dw_apb_i2c operations. disabling a restart does not allow the master to perform the following functions: ? send multiple bytes per transfer (split) ? change direction within a transfer (split) ? send a start byte ? perform any high-speed mode operation ? perform combined format transfers in 7- or 10-bit addressing modes (split for 7 bit) ? perform a read operation with a 10-bit address split operations are broken down into multiple dw_apb_i2c transfers with a stop and start condition in between. the other operations are not performed at all and result in setting tx_abrt. reset: ic_restart_en 4 ic_10bitaddr_master r/w this bit controls whether the dw_apb_i2c starts its transfers in 10-bit addressing mode when acting as a master. 0: 7-bit addressing 1: 10-bit addressing reset: 0
rock2 data sheet v1.1 08/04/06 rockchip electronics 77 of 128 3 ic_10bitaddr_slave r/w when acting as a slave, this bit controls whether the dw_apb_i2c responds to 7- or 10-bit addresses. 0: 7-bit addressing. 1: 10-bit addressing. reset: 0 2:1 speed r/w controls at which speed the dw_apb_i2c operates: 0: illegal; 1: standard mode (100 kbit/s) 2: fast mode (400 kbit/s) reset: 2 0 master_mode r/w this bit controls whether the dw_apb_i2c master is enabled or not. the slave is always enabled. 0: master disabled 1: master enabled reset: ic_master_mode ic_tar i 2 c target address register bits name r/w description 15:12 reserved n/a reserved. 11 special r/w this bit indicates whether software would like to perform a general call or start byte i 2 c command. 0: ignore bit 10 gc_or_startand use ic_tar normally 1: perform special i 2 c command as specified in gc_or_startbit reset: 0x0 10 gc_or_start r/w if bit 11 special is set to 1, then this bit indicates whether a general call or start byte command is to be performed by the dw_apb_i2c . 0: general call address ? after issuing a general call, only writes may be performed. attempting to issue a read command results in setting tx_abrt. the dw_apb_i2c remains in general call mode until the specialbit value is cleared. 1: start byte reset: 0x0 9:0 ic_tar r/w this is the target address for any master transactions. reset: ic_default_tar_slave_addr, which indicates loopback mode ic_sar : i 2 c slave address register bits name r/w description 15:10 reserved n/a reserved.
rock2 data sheet v1.1 08/04/06 rockchip electronics 78 of 128 9:0 ic_sar r/w the ic_sar holds the slave address when the i 2 c is operating as a slave. ic_sar holds the slave address to which the dw_apb_i2c responds. for 7-bit addressing, only ic_sar[6:0] is used. this register can be written only when the i 2 c interface is disabled, which corresponds to the ic_enable register being set to 0. writes at other times have no effect. reset: 0x55 ic_data_cmd i 2 c rx/tx data buffer and command register bits name r/w description 15:9 reserved n/a reserved 8 cmd r/w this bit controls whether a read or a write is performed. 1 = read. 0 = write. for reads, the lower 8 (dat) bits are ignored by the dw_apb_i2c . however, if the apb_data_width is 8, this ?dummy? write is still required as there is coherency in this register. reading this bit returns 0. attempting to perform a read operation after a general call command has been sent results in tx_abrt unless the special bit in the ic_tar register has been cleared. if this bit is written to a ?1? after receiving rd_req, then a tx_abrt occurs. reset: 0x10 7:0 dat r/w this register contains the data to be transmitted or received on the i 2 c bus. read these bits to read out the data received on the i 2 c interface. write these bits to send data out on the i 2 c interface. reset: 0x0 ic_ss_scl_hcnt: standard speed i 2 c clock scl high count register bits name r/w description 15:0 ic_ss_scl_ hcnt r/w 1 this register must be set before any i 2 c bus transaction can take place to ensure proper i/o timing. this register sets the scl clock high-period count for standard speed. the minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. reset : 0x64 ic_ss_scl_lcnt: standard speed i 2 c clock scl low count register
rock2 data sheet v1.1 08/04/06 rockchip electronics 79 of 128 bits name r/w description 15:0 ic_ss_scl_lcnt r/w 1 this register must be set before any i 2 c bus transaction can take place to ensure proper i/o timing. this register sets the scl clock low period count for standard speed. the minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. reset : 0x80 ic_fs_scl_hcnt: fast speed i 2 c clock scl high count register bits name r/w description 15:0 ic_fs_scl_hcnt r/w 1 this register must be set before any i 2 c bus transaction can take place to ensure proper i/o timing. this register sets the scl clock high-period count for fast speed. it is used in high-speed mode to send the master code and start byte or general call. the minimum valid value is 6; reset: 0x10 ic_fs_scl_lcnt: fast speed i 2 c clock scl low count register bits name r/w description 15:0 ic_fs_scl_lcnt r/w 1 this register must be set before any i 2 c bus transaction can take place to ensure proper i/o timing. this register sets the scl clock low period count for fast speed. it is used in high-speed mode to send the master code and start byte or general call. the minimum valid value is 8; reset: 0x22 ic_rx_tl: i 2 c receive fifo threshold register bits name r/w description 15:8 reserved n/a reserved. 7:0 rx_tl r/w receive fifo threshold level controls the level of entries (or above) that triggers the rx_full interrupt. the valid range is 0-3, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. if an attempt is made to do that, the actual value set will be the maximum depth of the buffer. a value of 0 sets the threshold for 1 entry, and a value of 3 sets the threshold for 4 entries. reset: ic_rx_tl=2
rock2 data sheet v1.1 08/04/06 rockchip electronics 80 of 128 ic_tx_tl: i 2 c transmit fifo threshold register bits name r/w description 15:8 reserved n/a reserved. 7:0 tx_tl r/w transmit fifo threshold level controls the level of entries (or below) that trigger the tx_empty interrupt. the valid range is 0-3, with the additional restriction that it may not be set to value larger than the depth of the buffer. if an attempt is made to do that, the actual value set will be the maximum depth of the buffer. a value of 0 sets the threshold for 0 entries, and a value of 3 sets the threshold for 4 entries. reset : ic_tx_tl=1 ic_enable: i 2 c enable register bits name r/w description 15:1 reserved n/a reserved. 0 enable r/w controls whether the dw_apb_i2c is enabled. writing a 1 enables the dw_apb_i2c , and writing a 0 disables it. software should not disable the dw_apb_i2c while it is active. the activity bit can be polled to determine if the dw_apb_i2c is active. if the module was transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. if the module was receiving, the dw_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. in systems with asynchronous pclk and ic_clk (ic_clk_type = 1), there is a two ic_clk delay when enabling or disabling the dw_apb_i2c . reset: 0x0 ic_status: i 2 c status registe bits name r/w description 4 rff r receive fifo completely full. when the receive fifo is completely full, this bit is set. when the receive fifo contains one or more empty location, this bit is cleared. 0 ? receive fifo is not full 1 ? receive fifo is full reset: 0x0 3 rfne r receive fifo not empty. set when the receive fifo contains one or more entries and is cleared when the receive fifo is empty. this bit can be polled by software to completely empty the receive fifo. 0 ? receive fifo is empty 1 ? receive fifo is not empty reset: 0x0
rock2 data sheet v1.1 08/04/06 rockchip electronics 81 of 128 2 tfe r transmit fifo completely empty. when the transmit fifo is completely empty, this bit is set. when it contains one or more valid entries, this bit is cleared. this bit field does not request an interrupt. 0 ? transmit fifo is not empty 1 ? transmit fifo is empty reset: 0x1 1 tfnf r transmit fifo not full. set when the transmit fifo contains one or more empty locations, and is cleared when the fifo is full. 0 ? transmit fifo is full 1 ? transmit fifo is not full reset: 0x1 0 activity r i2c activity status. reset: 0x0 3.11.3 example software bits %smode,0 mov r0, ic_enable ! disable i2c mov r2, 0x0 st r2, r0 mov r0, ic_sar ! i2c slave addr: 10bits:[9:0], or 7bits:[6:0] mov r2, 0x55 st r2, r0 mov r0, ic_con ! [6]:slave_disable [5]:restart_en [4]:10bit_master ! [3]:10bit_slave [2:1]: speed [0]:master mov r2, 0b1100101 ! dis, rest_en, 7bit, 7bit, fast, master st r2, r0 mov r0,ic_tar ! [11]: special [10]: gc_star [9:0]: i2c_tar mov r2, 0x55 ! 0, 0, addr st r2, r0 mov r0, ic_fs_hcnt ! 0x10, (min:6) mov r2, 0x6 st r2, r0 mov r0, ic_fs_lcnt ! 0x22, (min:8) mov r2, 0x8 st r2, r0 mov r0, ic_enable ! enable i2c mov r2, 0x1 st r2, r0 mov r0, ic_data_cmd mov r2, 0x30 ! write addr st r2, r0 mov r0, ic_data_cmd mov r2, 0x33 !write data st r2, r0 call dela y_300nop ! wait for ready ?????? mov r0, ic_data_cmd mov r2, p_add_ccr ! write addr of ccr
rock2 data sheet v1.1 08/04/06 rockchip electronics 82 of 128 st r2, r0 mov r0, ic_data_cmd mov r2, 0b00010010 ! write data to ccr: 44.1k dac and 32k adc st r2, r0 call delay_300nop mov r0, ic_data_cmd mov r2, p_add_cr2 ! write addr of cr2 st r2, r0 mov r0, ic_data_cmd ! write data to cr2 mov r2, 0b01011000 ! [6:5]: dac 20bits; [4:3]: adc 24bits; st r2, r0 ! [2]: adc_hpf; [1:0]: insel line1 call delay_300nop mov r5, p_add_cr2 mov r0, ic_data_cmd st r5, r0 !write cmd addr mov r7,0x100 !read cmd st r7,r0 call delay_300nop !wait for data ready wait123: mov r0, ic_status ! [4]:rff, [3]:rfne, [2]:tfe, [1]tfnf, [0]:activity ld r2, r0 mov r3, 0b01000 ! test rfne and r2, r3 cmp r2, r3 bz check_i2c_rxne_ok ! ready br wait123 check_i2c_rxne_ok: mov r0, ic_data_cmd ld r7, r0 !read data to dsp
rock2 data sheet v1.1 08/04/06 rockchip electronics 83 of 128 3.12 codec 3.12.1 overview single +1.8v (from 1.6v to 2.0v) power supply for the analog part separate power-down modes for adc and dac 24-/20-/18-/16-bit programmable word length serial audio interface i2dsp for digital audio data, i2c bridge for control data 2 stereo line inputs and one mic input with 85db a-weighted snr input gain range from 0db to 22.5db with 1.5db steps (4-bit programmable gain) output load down to 16 ohm with capacitor less connection and 90db a-weighted snr output dac path gain range from +6db to -32db (5-bit programmable gain) mixer function with programmable gains programmable sampling frequency fs betw een 8/11.025/16/22.05/32/44.1/48 khz
rock2 data sheet v1.1 08/04/06 rockchip electronics 84 of 128 3.12.2 register aicr: audio interface control register bit 1: dac_i2s: working mode of the dac digital serial audio interface 0= dsp mode, only dsp mode bit 0: adc_i2s: working mode of the adc digital serial audio interface 0= dsp mode, only dsp mode cr1: control register 1 bit 7: jack : output jack plug detection status 0= no jack 1= output jack present bit 6: mono : stereo-to-mono conversion for dac path 0= stereo 1= mono bit 5: dac_mute : dac soft mute mode 0= inactive 1= puts the dac in soft mute mode (internal input mute) bit 4: dac_deemp : dac de-emphasize filter enable 0= inactive 1= drives the internal input deemph bit 3: dacsel : mixer input selection 0= dac output ignored in input of the mixer 1= dac output selected as an input of the mixer (internal input dacsel) bit 2: bypass1 : mixer input selection (line 1) 0= bypass path ignored in input of the mixer 1= bypass path selected as an input of the mixer (internal input dacsel) bit 1: bypass2 : mixer input selection (line 2) 0= bypass path ignored in input of the mixer 1= bypass path selected as an input of the mixer (internal input dacsel) bit 0: sidetone : mixer input selection 0= sidetone path ignored in input of the mixer 1= sidetone path selected as an input of the mixer (internal input dacsel)
rock2 data sheet v1.1 08/04/06 rockchip electronics 85 of 128 cr2: control register 2 bit 7: ccmc : output short circuit detection status ? reserved for future use 0= inactive 1= indicates that a short circuit has been detected by the output stage. the conditions that reset the flag are given in the section 4.10. bit 6-3: dac_adwl[1:0], adc_adwl[1:0] : audio data word length: (internal input adwl) for respectively dac and adc paths 00 = 16-bit word length data 01 = 18-bit word length data 10 = 20-bit word length data 11 = 24-bit word length data bit 2: adc_hpf : adc high pass filter enable 0= inactive 1= enables the adc high pass filter (internal input hpf_en) bit 1-0: insel[1:0] : selection of the signal converted by the adc 00 = line 1 input 01 = line 2 input 10 = microphone input 11 = mixer output ccr: control clock register bit 7: quartz : selection of the mclk frequency 0= 12 mhz, only 12mhz can be select bit 6-4: dfreq[2:0]: selection of the dac sampling rate (fs) the sampling frequency value is given in the freq[2:0] table bit 2-0: afreq[2:0]: selection of the adc sampling rate (fs) the sampling frequency value is given in the freq[2:0] table freq[2:0] sampling rate (fs) 000 48khz 001 44.1khz 010 32khz 011 22.05khz 100 16khz 101 11.025khz 110 8khz 111 8khz
rock2 data sheet v1.1 08/04/06 rockchip electronics 86 of 128 pmr1: power mode register 1 bit 7: sb_dac : dac power-down mode 0= active 1= power-down bit 6: sb_out : output stage and mixer power-down mode 0= active 1= power-down bit 5: sb_mc : output stage common mode buffer power-down 0= active (capacitor less headphone output configuration) 1= power-down (line output configuration) bit 4: sb_adc : adc power-down mode 0= active 1= power-down bit 3: sb_in1 : line 1 input conditioning circuitry power-down mode 0= active 1= power-down bit 2: sb_in2 : line 2 input conditioning circuitry power-down mode 0= active 1= power-down bit 1: sb_mic : microphone input conditioning circuitry power-down mode 0= active 1= power-down bit 0: sb_ind : mixer to adc circuitry power-down mode 0= active 1= power-down pmr2: power mode register 2 bit 7-6: lrgi, rlgi: pgatm input gain coupling 00: left and right channels gains are independent, respectively given by gil and gir 10: left and right channels gain is given by gil 01: left and right channels gain is given by gir 11: left and right channels gain is given by gil bit 5-4: lrgod, rlgod: dac mixing gain coupling 00: left and right channels gains are independent, respectively given by godl and godr 10: left and right channels gain is given by godl 01: left and right channels gain is given by godr 11: left and right channels gain is given by godl bit 3: gim : microphone amplifier gain control 0= 20 db gain 1= 0 db gain
rock2 data sheet v1.1 08/04/06 rockchip electronics 87 of 128 bit 1: sb : complete power-down mode 0= normal mode (active) 1= complete power-down bit 0 sb_sleep : sleep mode 0= normal mode (active) 1= sleep mode cgr1: control gain register n1 bit 7-4: godr[3:0]: dac mixing right channel gain programming value bit 3-0: godl[3:0]: dac mixing left channel gain programming value cgr2: control gain register n2 bit 7-6: lrgob1, rlgob1: line 1 mixing gain coupling 00: left and right channels gains are independent, respectively given by gobl1 and gobr1 10: left and right channels gain is given by gobl1 01: left and right channels gain is given by gobr1 11: left and right channels gain is given by gobl1 bit 4-0: gobl1[4:0]: line 1 mixing left channel gain programming value cgr3: control gain register n3 bit 4-0: gobr1[4:0]: line 1 mixing right channel gain programming value cgr4: control gain register n4 bit 7-6: lrgob2, rlgob2: line 2 mixing gain coupling 00: left and right channels gains are independent, respectively given by gobl2 and gobr2 10: left and right channels gain is given by gobl2 01: left and right channels gain is given by gobr2 11: left and right channels gain is given by gobl2 bit 4-0: gobl2[4:0]: line 2 mixing left channel gain programming value
rock2 data sheet v1.1 08/04/06 rockchip electronics 88 of 128 cgr5: control gain register n5 bit 4-0: gobr2[4:0]: line 2 mixing right channel gain programming value cgr6: control gain register n6 bit 7-6: lrgos, rlgos: microphone mixing gain coupling 00: left and right channels gains are independent, respectively given by gosl and gosr 10: left and right channels gain is given by gosl 01: left and right channels gain is given by gosr 11: left and right channels gain is given by gosl bit 4-0: gosl[4:0]: microphone mixing left channel gain programming value cgr7: control gain register n7 bit 4-0: gosr[4:0]: microphone mixing right channel gain programming value cgr8: control gain register n8 bit 7-6: lrgo, rlgo: output stages gain coupling 00: left and right channels gains are independent, respectively given by gol and gor 10: left and right channels gain is given by gol 01: left and right channels gain is given by gor 11: left and right channels gain is given by gol bit 4-0: gol[4:0]: output stage left channel gain programming value cgr9: control gain register n9 bit 4-0: gor[4:0]: output stage right channel gain programming value
rock2 data sheet v1.1 08/04/06 rockchip electronics 89 of 128 cgr10: control gain register n10 bit 7-4: gil[3:0]: adc left channel pgatm input gain programming value drives the internal bus gil[3:0] bit 3-0: gir[3:0]: adc right channel pgatm input gain programming value drives the internal bus gir[3:0] tr1: test register n1 bit 7: stbyo : drives the internal input stbyo 0 in normal mode bit 6: stbyi : drives the internal input stbyi 0 in normal mode bit 5: tstdac : drives the internal input tstdac 0 in normal mode bit 4: tstadc : drives the internal input tstadc 0 in normal mode bit 3: test : test mode 0 in normal mode bit 2: stopull : disables the input circuitry starting system 0 in normal mode bit 1: nosc : disable the output short circuit protection 0 in normal mode bit 0: clkdiv4 : clock test mode 0 in normal mode tr2: test register n2 bit 7: echopdac : dac chopper control 1 in normal mode
rock2 data sheet v1.1 08/04/06 rockchip electronics 90 of 128 bit 6: faendac : flow adapter command control bit (dac path) 0: inactive 1: enables the flow adapter working mode bit 7: nencomp : biasing bit control 0 in normal mode bit 4: faenadc : flow adapter command control bit (adc path) 0: inactive 1: enables the flow adapter working mode bit 3: echopadc : adc chopper control 1 in normal mode bit 2: hipas : adc ntf test control 0 in normal mode bit 1: no_rst : adc auto reset control 0 in normal mode bit 0: unstbl : adc unstabitity status 0: reset of the status bit 3.12.3 interface: i2dsp mode dac or adc lro is a one mclk cycle high-level pulse. dac or adc sdata transmission has to start one mclk cycle after lro rising edge, left channel first, from msb to lsb, then right channel, from msb to lsb. there is no delay between left and right channel transmission, so word length (16, 18, 20 or 24 bits data width) must be taken into account when emitting or receiving data.
rock2 data sheet v1.1 08/04/06 rockchip electronics 91 of 128 3.12.4 soft mute mode a soft mute is implemented in order to redu ce audible parasites when the dac enters or leaves the mute mode. the mute signal is internally synchronized by a mclk rising edge. a high level puts the dac in mute mode. this decreases progressively the gain in the digital part (dwl block) from 0db to - during 19.97 ms. after this time, the signal in output of the dac is equal to 0 whatever the value of the digital input data. during soft mute mode, the dac is still conv erting but the output final voltages (aoutl, aoutr) are equal to vref/2. in the opposite, when the mute input is tied to a low level again, the dac leaves the mute mode by increasing progressively the gain in the digital part from - to 0db during 19.97 ms. after this time, the dac returns in normal mode. do not change the level of mute while the effect of the previous change is not reached, i.e. 20.48 ms (working not guaranteed). when the dac is in the gain up mode, do not enter in stand-by mode while the dac has not completely settled to the normal mode, i.e. 20.74 ms (working not guaranteed). 3.12.5 power-down and sleep mode ten stand-by inputs allow putting independently the different parts of hicodlv-9001 in power-down mode. two other stand-by inputs are available for test purpose: stbyi and stbyo. different working modes are sum-up in the following table (non exhaustive table):
rock2 data sheet v1.1 08/04/06 rockchip electronics 92 of 128 during the sleep mode and the complete power-down mode, the main clock mclk may be stopped to reduce the power consumption to the leakage currents only. in other modes, the main clock mclk must not be stopped.
rock2 data sheet v1.1 08/04/06 rockchip electronics 93 of 128 3.13 gpio ports 3.13.1 overview rock2 has 40 multi-functional gpio (general-pur pose input/output) port pins organized into 4 port groups: each port can be easily configured by software to meet various system configuration and design requirements. these multi-functional pins need to be properly conf igured before their use. if a multiplexed pin is not used as a dedicated functional pin, th is pin can be configured as gpio ports. the initial pin states, before pin configurations, are configured elegantly to avoid some problems. 3.13.2 block diagram
rock2 data sheet v1.1 08/04/06 rockchip electronics 94 of 128 3.13.3 block i/os i/o description register files interface pcon0[16:0] i port0 control pdat0[7:0] i/o port0 data pcon1[16:0] i port1 control pdat1[7:0] i/o port1 data pcon2a[16:0] i port2 control pdat2[15:0] i/o port2 data pcon2b[16:0] i port2 control pcon3[16:0] i port3 control pdat3[7:0] i/o port3 data extintr [7:0] i interrupt control register file interface i/os total: application interface p0(8) i/o p0 port p1(8) i/o p1 port p2(16) i/o p2 port p3(8) i/o p3 port table 1. port configuration overview selectable pin functions port 0 function 1 function 2 function 3 pin no gpio pin name i/o module pin name i/o module p0.0 55 input/output int0 i p0.1 56 input/output int1 i p0.2 57 input/output int2 i p0.3 58 input/output int3 i p0.4 59 input/output p0.5 60 input/output p0.6 61 input/output p0.7 62 input/output
rock2 data sheet v1.1 08/04/06 rockchip electronics 95 of 128 selectable pin functions port 1 function 1 function 2 function 3 pin no. gpio pin name i/o module pin name i/o module p1.0 65 input/output norcs o nor flash p1.1 66 input/output sda i/o i2c p1.2 67 input/output scl i/o i2c p1.3 68 input/output i2smclk o i2d p1.4 69 input/output dac_lrck i/o i2d p1.5 70 input/output adc_lrck i/o i2d p1.6 71 input/output sdi i i2d p1.7 72 input/output sdo o i2d selectable pin functions port 2 function 1 function 2 function 3 pin no. gpio pin name i/o module pin name i/o module p2.0 22 input/output sddo i sdmmc p2.1 23 input/output sddi o sdmmc p2.2 24 input/output sdclk o sdmmc p2.3 25 input/output sdcs o sdmmc fce1 o flash p2.4 26 input/output a0 o sdram p2.5 27 input/output a1 o sdram p2.6 28 input/output a2 o sdram p2.7 29 input/output a3 o sdram p2.8 43 input/output wen o sdram p2.9 44 input/output casn o sdram p2.10 45 input/output rasn o sdram p2.11 46 input/output csn o sdram p2.12 47 input/output p2.13 48 input/output pwm0 o pwm p2.14 49 input/output pwm1 o pwm p2.15 50 input/output pwm2 o pwm
rock2 data sheet v1.1 08/04/06 rockchip electronics 96 of 128 selectable pin functions port 3 function 1 function 2 function 3 pin no. gpio pin name i/o module pin name i/o module p3.0 120 input/output d8 i/o p3.1 121 input/output d9 i/o p3.2 122 input/output d10 i/o p3.3 123 input/output d11 i/o p3.4 124 input/output d12 i/o p3.5 125 input/output d13 i/o p3.6 126 input/output d14 i/o p3.7 127 input/output d15 i/o 3.13.4 register descriptions port control descriptions port configuration regi ster (pcon0 ? pcon3) in rock2, most pins are multiplexed, and t he pconn (port control register) determines which function is used for each pin. port data register (pdat0 ? pdat3) if ports are configured as output ports, data can be written to the corresponding bit of pdatn. if ports are configured as input ports, the data can be read from the corresponding bit of pdatn. external interrupt control register the port0.0-3 external interrupts support various trigger mode: the trigger mode can be configured as falling-edge trigger and rising-edge trigger. because each external interrupt pin has an integrated digital noise filter, the interrupt controller can recognize the request signal that lasts longer than 2 clocks.
rock2 data sheet v1.1 08/04/06 rockchip electronics 97 of 128 gpio ports special function registers register address r/w description reset value pcon0 0x0001_ee80 r/w configures the pins of port 0 0x0000 0000 pdat0 0x0001_ee88 r/w the data register for port 0 undefined pcon1 0x0001_ee90 r/w configures the pins of port 1 0x0000 0000 pdat1 0x0001_ee98 r/w the data register for port 1 undefined pcon2a 0x0001_eea0 r/w configures the pins of port 2[7:0] 0x0000 0000 pcon2b 0x0001_eea4 r/w configures the pins of port 2[15:8] 0x0000 0000 pdat2 0x0001_eea8 r/w the data register for port 2 undefined pcon3 0x0001_eeb0 r/w configures the pins of port 3 0x0000 0000 pdat3 0x0001_eeb8 r/w the data register for port 3 undefined extintr 0x0001_eec0 r/w external interrupt control register 0x0000 0000 port 0 control registers (pcon0, pdat0) pcon0 bit description p0.0 [1:0] 00 = input, pull up 10 = int0, pull up 01 = output, pull up 11 = input, pull up p0.1 [3:2] 00 = input, pull up 10 = int1, pull up 01 = output, pull up 11 = input, pull up p0.2 [5:4] 00 = input, pull up 10 = int2, pull up 01 = output, pull up 11 = input, pull up p0.3 [7:6] 00 = input, pull up 10 = int3, pull up 01 = output, pull up 11 = input, pull up p0.4 [9:8] 00 = input, pull up 10 = input 01 = output 11 = input, pull up p0.5 [11:10] 00 = input, pull up 10 = input 01 = output 11 = input, pull up p0.6 [13:12] 00 = input, pull up 10 = input 01 = output 11 = input, pull up p0.7 [15:14] 00 = input, pull up 10 = input 01 = output 11 = input, pull up
rock2 data sheet v1.1 08/04/06 rockchip electronics 98 of 128 pdat0 bit description p0[7:0] [7:0] when the port is configured as out put port, the pin state is the same as the corresponding bit when the port is configured as functional pin, the undefined value will be read. port 1 control registers (pcon1, pdat1) pcon1 bit description p1.0 [1:0] 00 = output, norcsn 10 = input 01 = output 11 = input, pull up p1.1 [3:2] 00 = input, pull up 10 = input 01 = output 11 = i2c_sda p1.2 [5:4] 00 = input, pull up 10 = input 01 = output 11 = i2c_scl p1.3 [7:6] 00 = input, pull up 10 = input 01 = output 11 = i2smclk p1.4 [9:8] 00 = input, pull up 10 = i2d_dac_lrck output 01 = output 11 = i2d_dac_lrck input p1.5 [11:10] 00 = input, pull up 10 = i2d_adc_lrck output 01 = output 11 = i2d_adc_lrck input p1.6 [13:12] 00 = input, pull up 10 = input 01 = output 11 = i2d_sdi p1.7 [15:14] 00 = input, pull up 10 = input 01 = output 11 = i2d_sdo pdat1 bit description p1[7:0] [7:0] when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
rock2 data sheet v1.1 08/04/06 rockchip electronics 99 of 128 port 2 control registers (pcon2, pdat2) pcon2a bit description p2.0 [1:0] 00 = sddo 10 = input 01 = output 11 = input p2.1 [3:2] 00 = sddi 10 = input 01 = output 11 = input p2.2 [5:4] 00 = sdclk 10 = input 01 = output 11 = input p2.3 [7:6] 00 = sdcs 10 = input 01 = output 11 = flash fce1 p2.4 [9:8] 00 = a0 10 = input 01 = output 11 = input p2.5 [11:10] 00 = a1 10 = input 01 = output 11 = input p2.6 [13:12] 00 = a2 10 = input 01 = output 11 = input p2.7 [15:14] 00 = a3 10 = input 01 = output 11 = input pcon2b bit description p2.8 [1:0] 00 = wen 10 = input 01 = output 11 = input p2.9 [3:2] 00 = casn 10 = input 01 = output 11 = input p2.10 [5:4] 00 = rasn 10 = input 01 = output 11 = input p2.11 [7:6] 00 = csn 10 = input 01 = output 11 = input p2.12 [9:8] 00 = input 10 = input 01 = output 11 = input p2.13 [11:10] 00 = input 10 = input 01 = output 11 = pwm p2.14 [13:12] 00 = input 10 = input 01 = output 11 = pwm p2.15 [15:14] 00 = input 10 = input 01 = output 11 = pwm
rock2 data sheet v1.1 08/04/06 rockchip electronics 100 of 128 pdat2 bit description p2[15:0] [15:0] when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read. port 3 control registers (pcon3, pdat3) pcon3 bit description p3.0 [1:0] 00 = d8, pull up 10 = input 01 = output 11 = input, pull up p3.1 [3:2] 00 = d9, pull up 10 = input 01 = output 11 = input, pull up p3.2 [5:4] 00 = d10, pull up 10 = input 01 = output 11 = input, pull up p3.3 [7:6] 00 = d11, pull up 10 = input 01 = output 11 = input, pull up p3.4 [9:8] 00 = d12, pull up 10 = input 01 = output 11 = input, pull up p3.5 [11:10] 00 = d13, pull up 10 = input 01 = output 11 = input, pull up p3.6 [13:12] 00 = d14, pull up 10 = input 01 = output 11 = input, pull up p3.7 [15:14] 00 = d15, pull up 10 = input 01 = output 11 = input, pull up pdat3 bit description p3[7:0] [7:0] when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
rock2 data sheet v1.1 08/04/06 rockchip electronics 101 of 128 extintr (external interrupt polarity control register) the extintr register selects the trigger types among various level or edge trigger mode of the external interrupt. extintr bit description p0.0/int0 [1:0] trigger mode of the extint0. 00= falling edge triggered 10= falling or rising edge 0 1 = rising edge triggered 11= none p0.1/int1 [3:2] trigger mode of the extint1. 00= falling edge triggered 10= falling or rising edge 0 1 = rising edge triggered 11= none p0.2/int2 [5:4] trigger mode of the extint2. 00= falling edge triggered 10= falling or rising edge 0 1 = rising edge triggered 11= none p0.3/int3 [7:6] trigger mode of the extint3. 00= falling edge triggered 10= falling or rising edge 0 1 = rising edge triggered 11= none notes : if users want to change the trigger mode in the ex ternal interrupt mode, users are first required to switch the corresponding pin to input mode and then change the trigger mode.
rock2 data sheet v1.1 08/04/06 rockchip electronics 102 of 128 3.14 sd/mmc controller the secure digital card interface (sdci) can interface for sd memory card and multi media card (mmc). sd/mmc card interface register files sdclk figure 1. overview txfifo_vilid rxfifo_vilid sddo sdcs sddi sdciclk features ? supports multi media card specification version 3.1 ? supports sd memory card specification version 1.0 ? cards clock rate up to pclk ? 8 words (32 bytes) fifo (depth 8) for data transmit ? 8 words (32 bytes) fifo (depth 8) for data receive ? crc7 & crc16 generator/checker ? normal data transfer mode ? support for block and multi-block data read and write ? spi mode support clock requirement: sdciclk = pclk !!!note!!!: the dma function has disable, only dsp read/write. don?t use dma function.
rock2 data sheet v1.1 08/04/06 rockchip electronics 103 of 128 3.14.1 block diagram register file pclk domain sdciclk domain figure 2. block diagram resetn sdciclk sdci_ctrl[16:0] sdclk sddi sdcs sddo dat control shift register crc16 cmd control shift register crc7 clock control tx fifo rx fifo pclk sdci_tx[31:0] sdci_rx[31:0] sdci_cmd[16:0] sdci_resp[47:0] sdci_txfifo_vilid sdci_rxfifo_vilid 3.14.2 block i/os adc controller i/o description register file interface sdci_tx[31:0] i sd/mmc interface data transmit to external sd/mmc card sdci_rx[31:0] o sdci data receive from external sd/mmc card sdci_ctrl[15:0] i sdci control signal from dsp sdci_dctrl[15:0] i sdci data control signal from dsp sdci_cmd[15:0] i sdci command(cmd) signal from dsp sdci_arg[31:0] i sdci command(cmd) argument signal from dsp sdci_dlen[16:0] i sdci data block length signal from dsp sdci_token [15:0] i sdci data block transmit token signal from dsp sdci_resp0[31:0] o response data0 from external sd/mmc card sdci_resp0[7:0] o response data1 from external sd/mmc card
rock2 data sheet v1.1 08/04/06 rockchip electronics 104 of 128 sdci_sta[15:0] o adci transmit/receive status to dsp sdci_stac[15:0] i clear transmit/receive status from dsp register file interface i/os total: application interface sdciclk i sd card interface module clock input sdcs o external sd/mmc card select sddi o data output to external sd/mmc card sdclk o clock output to external sd/mmc card sddo i data input from external sd/mmc card sddo_en o data output enable sd_txfifo_vilid o sd/mmc card interface transmit fifo not full, to dma sd_rxfifo_vilid o sd/mmc card interface receive fifo not empty, to dma sdci operation in rock2, sdci select spi as transmit and receive function. a serial clock line (sdclk) is synchronized with the data output(sddi) and the data input(sddo). in which, sddo/sddi are directly conn ect to external sd card of sddo/sddi . sdci configuration after a hardware reset, the sdci pins are selected as spi mode. cmd path programming 1. (soft) write the argument value to sdci_arg register. 2. (soft) write the command information to sdci_cmd register. ? confirm the ready of command transmission flag of sdci_sta[0]. 3. (soft) write the command start bi t (cmdstr) to sdci_cmd register. (sdci hard) when sdci detected cmdstr == 1, begin transmitting the cmd, and then receive the response data from external sd card . during this progress, the sdci will response the progress to sdci_sta[4:1], which can be read by dsp and decide the next progress. 4. (soft) check the status of sdci command operation by dsp. ? command transmission is in progress, the sdci_sta[1] is set. ? command transmission is completed, the sdci_sta[2] is set. ? response reception is in prog ress, the sdci_sta[3] is set. ? response reception is completed, the sdci_sta[4] is set. 5. (soft) check the status of response if there is time-out error occur 6. (soft) check the card response, read from sdci_resp1~0 register. 7. (soft) clear the corresponding flag of the sdci_sta register by write the sdci_stac register.
rock2 data sheet v1.1 08/04/06 rockchip electronics 105 of 128 hard core progress : in step 3. when sdci detected cmdstr == 1 1) reset crc7 to 000,0000b 2) transmit the 6bit cmd in sdci_cmd, 32bit command argument in sdci_arg 3) transmit the 7 bits of crc7 and one clock of end(1). 4) start receiving the response data from external sd card. during this progress, the sdci will response the progress to sdci_sta[4:1], which can be read by dsp and decide the next progress. at receiving response state, the sdclk must be byte aligned (multiples of 8 clocks). it must count the clocks and compare to ncr_nbr (at sdci_cmd register), if the counter is bigger then ncr(64 clock cycle), or nbr(8 clock cycle), but the response data have not been receive, an error of response (restoute) is occar.
rock2 data sheet v1.1 08/04/06 rockchip electronics 106 of 128 sdciclk cmdstr sdci_sta[1] cmdpro cmdend sdci_sta[2] respro sdci_sta[3] clear by clr_cmdend resend sdci_sta[4] clear by clr_resend sdci_stac[2] clr_cmdend sdci_stac[4] clr_resend sdci_sta[0] sdclk fig3. write cmd timing sdcs sd enable hhh sddi output to sd card 01 cmd5 sddo hhh lsb crc0 0/h/? receive from sd card hhh hhh dat path programming (not use dma) -operation of addressed data transfer commands (adtc) 1. (soft) write the data block length to the sdci_dctrl register. 2. (soft) fifo reset by writing the sdci_dctrl register. 3. (soft and hard core progress) do cmd path programming
rock2 data sheet v1.1 08/04/06 rockchip electronics 107 of 128 4. (soft) write the data transmission start bit datstr to sdci_dctrl[2] register(only data write operation). 5. (soft) when write operation, write tx data to sdci_tx register while txfifo is available by checking txfifo_nfull in sdci_sta[13:12]. 6. (soft) when read operation, read rx data to sdci_rx register while rxfifo is available by checking rxfifo_nempty in sdci_sta[11:10]. 7. (soft) check the status of sdci data operation. ? data transmission/reception is in progress, the sdci_sta[5] is set. ? data block transmission/reception is completed, the sdci_sta[6] is set. ? data crc data transmission/reception is completed, the sdci_sta[7] is set. ? crc status token reception is completed, the sdci_sta[8] is set, only write command. ? card busy state, the sdci_sta[9] is set. 8. (soft) check the status of data transfer 9. (soft) clear the corresponding flag of the sdci_sta register by write the sdci_stac register. 10. if multiple data block transfer, repeat 4~9. hard core progress : in step 4. in transmit progress, when sdci detected datstr == 1 1) begin transmitting the token, when the token have been transmit ok, sdci resets the crc16 to 0x0000. 2) start transmit the data block (length of sdci_dlen ) . 3) transmit the 2 bytes of crc16. 4) start reading response data from external sd card. which can be read by dsp and decide the next progress. during this progress, the sdci will response the state to sdci_sta[8:5], which can be read by dsp and decide the next progress. in receive progress, when sdci detected datstr == 1 1) begin reading the data block, when a block (length of sdci_dlen ) has been receive ok, save the data of crc16 to the sdci_crc16 register. 2) receive the 16bit crc16 data. 3) compare the 16bit crc16 data to sdci_crc16 register, if they equal, clear the crc16e in sdci_sta register. during this progress, the sdci will response t he state to sdci_sta[8:5], which can be read by dsp and decide the next progress.
rock2 data sheet v1.1 08/04/06 rockchip electronics 108 of 128 datstr sdci_sta[5] datpro datend sdci_sta[6] dat crc end sdci_sta[7] clear by clr_datend crc staend sdci_sta[8] clear by clr_crc_staend sdci_stac[6,7,8] clr_...end sdci_sta[0] card busy sdci_sta[9] clear by clr_dat_crcend fig4. data transmit/recive timing sdciclk sdclk hhh sddi output data to sd card sddo hhh crc16 data lsb receive data from sd card crc0 crc1 crc15 data msb crc16 crc0 crc1 crc15 card busy hhh hhh data msb data lsb clock from clock gen fifo model: (using dsp) when transmit, dsp first check signal tx_fifo_ nfull, if it is high, then transmit data to txfifo0-7. if the txfifos are full, it pulls tx_fifo_nfull to low, dsp waiting a high of tx_fifo_nfull for next transmition. as the shift register reads a data from txfifos, tx_fifo_nfull comes high. when receive, the shift register puts data to the rxfifos, dsp first check signal rx_fifo_nempty, if it is high, then reads data from rxfifos. if it reads all the data, sdci will reset rx_fifo_nempty to low. when t he rxfifos are full, the rx_fifo_full will be high, sdci stops receiving data from sd card (hold down the sdclk).
rock2 data sheet v1.1 08/04/06 rockchip electronics 109 of 128 txfifo7 (32bit) txfifo4 (32bit) txfifo5 (32bit) txfifo6 (32bit) txshift reg (32bit) rxfifo7 (32bit) rxfifo4 (32bit) rxfifo5 (32bit) rxfifo6 (32bit) rxshift reg (32bit) fig 5. fifo block dma dma rxfifo3 (32bit) rxfifo0 (32bit) rxfifo1 (32bit) rxfifo2 (32bit) txfifo3 (32bit) txfifo0 (32bit) txfifo1 (32bit) txfifo2 (32bit) sd_rxfifo_vilid sd_txfifo_vilid transmit receive rx_fifo_nempty dsp dsp tx_fifo_nfull sdci_rx (32bit) sdci_tx (32bit) the write data block length is only 512 bytes, which value is in the register sdci_dlen. 3.14.3 register descriptions sdci register base address = 0x0001_ef00 register name width offset read/ write register name initial value sdci_ctrl 16bit 0x00 r/w control register 0x0000 sdci_dctrl 16bit 0x04 r/w data control register 0x0000 sdci_dlen 16bit 0x08 r/w data control register 0x0000 sdci_token 16bit 0x0c r/w data block token 0x0000 sdci_cmd 16bit 0x10 r/w command register 0x0000 sdci_arg 32bit 0x14 r/w argument register 0x0000_0000 sdci_stac 16bit 0x18 w status clear register 0x0000 sdci_sta 16bit 0x1c r status register 0x3000
rock2 data sheet v1.1 08/04/06 rockchip electronics 110 of 128 sdci_resp0 32bit 0x20 r response register0 0x0000_0000 sdci_resp1 8bit 0x24 r response register1 0x00 sdci_tx 32bit 0x28 r/w data transmit register 0x0000_0000 sdci_rx 32bit 0x2c r/w data receive register 0x0000_0000 sdci_crc16 16bit 0x30 r/w crc16 buffer register 0x0000_0000 sd/mmc clock control register (sdclkcon): (this register is in the clock module) sdclkcon bit description initial state reserved [15:8] reserved - sdciclk_div [7:0] 8-bit prescaler value the input clock is pclk sdciclk = pclk / (sdclk_div + 1) 0000,0000b sd/mmc control register (sdci_ctrl) name bit description reserved 15:5 sd_csen 4 sd card select 0 = disable sdcs, pull the sdcs pin high 1 = enable sdcs, reset the sdcs pin low dma_req_con 3 select dma request condition, only read command 0 = dma request when receive fifo is not empty. 1 = dma request when receive fifo is full. dmaen 2 dma enable 0 = dma disable 1 = dma enable card_type 1 select the card type 0 = sd card 1 = mm card sdcien 0 sdci block enable 0 = disable the sdci 1 = enable the sdci
rock2 data sheet v1.1 08/04/06 rockchip electronics 111 of 128 sd/mmc data control (sdci_dctrl) register name bit description reserved 15:3 datstr 2 start the data transfer, automatically cleared. 0 = no effect 1 = data transmission start rxfiforst 1 reset the receive fifo. 0 = no effect 1 = reset the receive fifo txfiforst 0 reset the transmit fifo. 0 = no effect 1 = reset the transmit fifo sd/mmc data length (sdci_dlen) register name bit description blk_len 15:0 determine the data block size (unit : byte) sd/mmc data token (sdci_token) register name bit description token 7:0 data block token sdci command (sdci_cmd) register name bit description taac 15:12 taac response clock cycle , 65536*(taac+1) cmdstr 11 start the command transfer, automatically cleared. only writable when sdci_sr[0] = 1. 0 = no effect 1 = command transmit start
rock2 data sheet v1.1 08/04/06 rockchip electronics 112 of 128 ncr_nbr 10 select the clock cycle command to response. 0 = ncr(<=64 clock cycle) 1 = nbr(<=8 clock cycle) res_format 9:8 select response format 00 = no response 01 = r1 (8bit), r1b(8bit+busy), data resp (8bit) 10 = r2 (16bit) 11 = r3 (40bit,r1+ocr) reserved 7 cmd_read 6 select the command type 0 = general command 1 = read data command cmd_num 5:0 set the command number sdci argument (sdci_arg) register name bit description argument 31:0 set the argument value sdci status clear (sdci_stac) register name bit description clr_ datcrc16e 15 clear datcrc16e at sdci_ sta register 0 = no effect 1 = clear the resende bit clr_restoute 14 clear restoute at sdcr_ sta register 0 = no effect 1 = clear the restoute bit reserved 13:9 clr_crc_staend 8 clear crc_staend at sdci_ sta register 0 = no effect 1 = clear the crc_staend bit clr_dat_crcend 7 clear dat_crcend at sdci_sta register 0 = no effect 1 = clear the dat_crcend bit
rock2 data sheet v1.1 08/04/06 rockchip electronics 113 of 128 clr_datend 6 clear dat_end at sdci_ sta register 0 = no effect 1 = clear the datend bit reserved 5 clr_resend 4 clear resend at sdci_ sta register 0 = no effect 1 = clear the resend bit reserved 3 clr_cmdend 2 clear cmdend at sdci_ sta register 0 = no effect 1 = clear the cmdend bit reserved 1:0 sdci status (sdci_sta) register clear condition: a : according to the sdci interface state. c : clear by write '1' to corresponding bit of sdci_stac. name bit description clear condit ion datcrc16e 15 receive data crc16 error 0 = no crc16 error occurs 1 = crc16 error occurs c restoute 14 response timeout error (ncr, nbr) 0 = no command to response timeout error occurs 1 = command to response timeout error occurs c tx_fifo_nfull 13 tx fifo full 0 = transmit fifo is full 1 = transmit fifo is not full a tx_fifo_empty 12 tx fifo empty 0 = transmit fifo is not empty 1 = transmit fifo is empty a rx_fifo_full 11 rx fifo full 0 = receive fifo is not full 1 = receive fifo is full a rx_fifo_nempty 10 rx fifo empty 0 = transmit fifo is empty 1 = transmit fifo is not empty a
rock2 data sheet v1.1 08/04/06 rockchip electronics 114 of 128 dat_busy 9 data line busy 0 = card is not busy 1 = card is busy this status is direct connected inverted sddo of card. a crc_staend 8 write data crc status token receive end 0 = crc status token reception is not ended 1 = crc status token reception is ended c dat_crcend 7 data crc transmit/receive end 0 = crc transmission/reception is not ended 1 = crc transmission/reception is ended c datend 6 data transmit/receive end 0 = data transmission/reception is not ended 1 = data transmission/reception is ended c datpro 5 data transfer in progress 0 = data transmission/reception is not in progress 1 = data transmission/reception is in progress a resend 4 response receive end 0 = response reception is not ended 1 = response reception is ended c respro 3 response receive in progress 0 = response reception is not in progress 1 = response reception is in progress a cmdend 2 command transfer end 0 = command transmission is not ended 1 = command transmission is ended c cmdpro 1 command transfer in progress 0 = command transmission is not in progress 1 = command transmission is in progress a cmdrdy 0 command ready 0 = command transfer is not ready 1 = command transfer is ready (sdci_cmd, sdci_arg set complete) a sdci response0 (sdci_resp0) register name bit description
rock2 data sheet v1.1 08/04/06 rockchip electronics 115 of 128 response0 31:0 the res_format [2:0] determines the value r1, r1b: response [7:0] , [31:8] == 0000,00 r2: response [15:00] , [31:16] == 0000 r3: response [31:00] sdci response1 (sdci_resp1) register name bit description response1 7:0 the res_format [2:0] determines the value r1, r1b: 00 r2: 00 r3: response [7:0] == r1 sdci data (sdci_tx) register name bit description sdci_tx 31:0 data buffer for transmit note: if data is not aligned to word (4byte), sdci_tx register value is following table(little_endian). write data sdci_tx[31:24] sdci_tx[13:16] sdci_tx[15:8] sdci_tx[7:0] 4n+1 byte write data[7:0] stuff bits stuff bits stuff bits 4n+2 byte write data[15:8] write data[7:0] stuff bits stuff bits 4n+3 byte write data[23:16] write data[15:8] write data[7:0] stuff bits sdci data (sdci_rx) register name bit description sdci_rx 31:0 data buffer for receive
rock2 data sheet v1.1 08/04/06 rockchip electronics 116 of 128 note: if data is not aligned to word(4byte), sdci_rx register value is following table (little_endian) read data sdci_rx[31:24] sdci_rx[13:16] sdci_rx[15:8] sdci_rx[7:0] 4n+1 byte 0x00 0x00 0x00 read data[7:0] 4n+2 byte 0x00 0x00 read data[15:8] read data[7:0] 4n+3 byte 0x00 read data[23:16] read data[15:8] read data[7:0] crc16 data (sdci_crc16) register name bit description sdci_crc16 15:0 the value of crc16 by the receive data
rock2 data sheet v1.1 08/04/06 rockchip electronics 117 of 128 4 programming information 4.1 address maps (memory spacing) dsp internal memory space dma_master1 low dsp_master2 high dsp_iram 0x0000_0000--0x0000_efff 60kw dsp_boot 0x0000_f000--0x0000_ffff 4kw dsp_dram 0x0000_0000--0x0000_efff 60kw system memory space module address usb 0x0001_e000--0x0001_e3ff 1kb 4 apb (0x0001_e400--0x0001_efff) 3kb 3 wdt 0x0001_e4000--0x0001_e7ff 1kb i2c 0x0001_e800--0x0001_ebff 1kb register file(apb) (0x0001_ec00--0x0001_efff) 1kb i2s 0x0001_ec00--0x0001_ec7f 128b pwm 0x0001_ec80--0x0001_ecff 128b 4-1.adc 0x0001_ed00--0x0001_ed7f 128b dc/dc 0x0001_ed80--0x0001_edff 128b clock/pll 0x0001_ee00--0x0001_ee7f 128b gpio 0x0001_ee80--0x0001_eeff 128b sd/mmc 0x0001_ef00--0x0001_ef7f 128b external (0x0001_f000--0x0001_fbff) (0x0000_0000--0x0001_dfff) (0x0020_0000--0x003f_ffff) 3kb 120kb 2mb 1 register file(ahb) 0x0001_f800--0x0001_f8ff 256b video 0x0001_f900--0x0001_f9ff 0x0001_0000--0x0001_dfff 256b 32kb flash_cs0 0x0001_fa00--0x0001_faff 0x0000_0000--0x0000_7fff 256b 32kb flash_cs1 0x0001_fb00--0x0001_fbff 0x0000_8000--0x0000_ffff 256b 32kb eprom 0x0001_f000--0x0001_f7ff 0x0020_0000--0x003f_ffff 2kb/bootrom 2mb dma 0x0001_fc00--0x0001_ffff 1kb 2 memory controller 0x0002_0000--0x0005_ffff 256kb 5 imem 0x0002_0000--0x0003_ffff 128kb/120kb dmem 0x0004_0000--0x0005_ffff 128kb/120kb sdram controller 0x0006_0000?0x0006_ffff 64kb 6 sdram 0x0400_0000--0x07ff_ffff 64m 7
rock2 data sheet v1.1 08/04/06 rockchip electronics 118 of 128 4.2 interrupt vector interrupt ? address p00_int 0 16 p01_int 1 15 p02_int 2 14 p03_int 3 13 pwm 4 12 timer0 5 11 timer1 6 10 dmac 7 9 wdt 8 8 - 9 7 usb 10 6 - 11 5 - 12 4 - 13 3 -dei 14 2 nmi 15 1 reset 16 0 4.3 registers #define mempcr 0xf807 #define gpoport 0xf806 #define dsp_stack 0xbfff #define lcd_data (0x1f900 )/2 #define lcd_reg (0x1f900+0x04)/2 #define flash0_data (0x1fa00 )/2 #define flash0_addr (0x1fa00+0x04)/2 #define flash0_cmd (0x1fa00+0x08)/2 #define flash1_data (0x1fb00 )/2 #define lcd_data1 0x10000 #define flash1_addr (0x1fb00+0x04)/2 #define flash1_cmd (0x1fb00+0x08)/2 #define ext_reg_base 0x1f800 #define ecc0 (ext_reg_base+0x00)/2 #define ecc1 (ext_reg_base+0x04)/2 #define ecc2 (ext_reg_base+0x08)/2 #define ecc3 (ext_reg_base+0x0c)/2 #define eccctl (ext_reg_base+0x10)/2 #define fmctl (ext_reg_base+0x14)/2 #define cfwait (ext_reg_base+0x18)/2 #define fmwait (ext_reg_base+0x1c)/2
rock2 data sheet v1.1 08/04/06 rockchip electronics 119 of 128 #define lcdwait (ext_reg_base+0x20)/2 #define sysctl (ext_reg_base+0x24)/2 #define sdram_base 0x4000000/2 #define dspmem_base 0x20000/2 #define usb_base 0x1e000/2 #define extmem_base 0x00000/2 #define extmem_base2 0x80000/2 #define i2c_base 0x1e800/2 #define wdt_base 0x1e400/2 #define dw_apb_i2c_base 0x1e800 #define ic_con (dw_apb_i2c_base + 0x00)/2 // r/w [5:0] 0x04 #define ic_tar (dw_apb_i2c_base + 0x04)/2 // r/w [11:0] 0x55 #define ic_sar (dw_apb_i2c_base + 0x08)/2 // r/w [9:0] 0x55 #define ic_hs_maddr (dw_apb_i2c_base + 0x0c)/2 #define ic_data_cmd (dw_apb_i2c_base + 0x10)/2 // r/w [8:0] 0x0 #define ic_ss_hcnt (dw_apb_i2c_base + 0x14)/2 // r/w [15:0] 0x60 #define ic_ss_lcnt (dw_apb_i2c_base + 0x18)/2 // r/w [15:0] 0x80 #define ic_fs_hcnt (dw_apb_i2c_base + 0x1c)/2 // r/w [15:0] 0x10 #define ic_fs_lcnt (dw_apb_i2c_base + 0x20)/2 // r/w [15:0] 0x22 #define ic_hs_hcnt (dw_apb_i2c_base + 0x24)/2 #define ic_hs_lcnt (dw_apb_i2c_base + 0x28)/2 #define ic_intr_stat (dw_apb_i2c_base + 0x2c)/2 #define ic_intr_mask (dw_apb_i2c_base + 0x30)/2 #define ic_raw_intr_stat (dw_apb_i2c_base + 0x34 )/2 #define ic_rx_tl (dw_apb_i2c_base + 0x38)/2 #define ic_tx_tl (dw_apb_i2c_base + 0x3c)/2 #define ic_clr_intr (dw_apb_i2c_base + 0x40)/2 #define ic_clr_rx_under (dw_apb_i2c_base + 0x44)/2 #define ic_clr_rx_over (dw_apb_i2c_base + 0x48)/2 #define ic_clr_tx_over (dw_apb_i2c_base + 0x4c)/2 #define ic_clr_rd_req (dw_apb_i2c_base + 0x50)/2 #define ic_clr_tx_abrt (dw_apb_i2c_base + 0x54)/2 #define ic_clr_rx_done (dw_apb_i2c_base + 0x58)/2 #define ic_clr_activity (dw_apb_i2c_base + 0x5c)/2 #define ic_clr_stop_det (dw_apb_i2c_base + 0x60)/2 #define ic_clr_start_det (dw_apb_i2c_base + 0x64)/2 #define ic_clr_gen_call (dw_apb_i2c_base + 0x68)/2 #define ic_enable (dw_apb_i2c_base + 0x6c)/2 #define ic_status (dw_apb_i2c_base + 0x70)/2 // r [4:0] 0x6 #define ic_txflr (dw_apb_i2c_base + 0x74)/2 #define ic_rxflr (dw_apb_i2c_base + 0x78)/2 #define ic_sreset (dw_apb_i2c_base + 0x7c)/2 #define ic_tx_abrt_source (dw_apb_i2c_base + 0x80)/2 #define ic_version_id (dw_apb_i2c_base + 0xf8)/2 #define ic_dma_cr (dw_apb_i2c_base + 0x88)/2 #define ic_dma_tdlr (dw_apb_i2c_base + 0x8c)/2 #define ic_dma_rdlr (dw_apb_i2c_base + 0x90)/2 #define i2cping_1bit_wr (ic_tar)/2 #define dmacbase 0x1fc00 // r/w width reset value #define dmar_sar0 (dmacbase+0x000)/2 // r/w 32 0x0 #define dmar_dar0 (dmacbase+0x008)/2 // r/w 32 0x0 #define dmar_ctl0 (dmacbase+0x018)/2 // r/w 64 0x00000002_00004825
rock2 data sheet v1.1 08/04/06 rockchip electronics 120 of 128 #define dmar_cfg0 (dmacbase+0x040)/2 // r/w 64 0x00000004_00000c00 #define dmar_sgr0 (dmacbase+0x048)/2 // r/w 32 0x0 #define dmar_dsr0 (dmacbase+0x050)/2 // r/w 32 0x0 #define dmar_sar1 (dmacbase+0x058)/2 // r/w 32 0x0 #define dmar_dar1 (dmacbase+0x060)/2 // r/w 32 0x0 #define dmar_ctl1 (dmacbase+0x070)/2 // r/w 64 0x00000002_00004825 #define dmar_cfg1 (dmacbase+0x098)/2 // r/w 64 0x00000004_00000c20 #define dmar_sgr1 (dmacbase+0x0a0)/2 // r/w 32 0x0 #define dmar_dsr1 (dmacbase+0x0a8)/2 // r/w 32 0x0 #define dmar_sar2 (dmacbase+0x0b0)/2 // r/w 32 0x0 #define dmar_dar2 (dmacbase+0x0b8)/2 // r/w 32 0x0 #define dmar_ctl2 (dmacbase+0x0c8)/2 // r/w 64 0x00000002_00004825 #define dmar_cfg2 (dmacbase+0x0f0)/2 // r/w 64 0x00000004_00000c40 #define dmar_sgr2 (dmacbase+0x0f8)/2 // r/w 32 0x0 #define dmar_dsr2 (dmacbase+0x100)/2 // r/w 32 0x0 #define dmar_rawblock (dmacbase+0x2c8)/2 // r 3 0x0 #define dmar_rawsrctran (dmacbase+0x2d0)/2 // r 3 0x0 #define dmar_rawdsttran (dmacbase+0x2d8)/2 // r 3 0x0 #define dmar_rawerr (dmacbase+0x2e0)/2 // r 3 0x0 #define dmar_rawtfr (dmacbase+0x2c0)/2 // r 3 0x0 #define dmar_statustfr (dmacbase+0x2e8)/2 // r 3 0x0 #define dmar_statusblock (dmacbase+0x2f0)/2 // r 3 0x0 #define dmar_statusblock (dmacbase+0x2f0)/2 // r 3 0x0 #define dmar_statussrctran (dmacbase+0x2f8)/2 // r 3 0x0 #define dmar_statusdsttran (dmacbase+0x300)/2 // r 3 0x0 #define dmar_statuserr (dmacbase+0x308)/2 // r 3 0x0 #define dmar_masktfr (dmacbase+0x310)/2 // r/w 3-3 0x0 #define dmar_maskblock (dmacbase+0x318)/2 // r/w 3-3 0x0 #define dmar_masksrctran (dmacbase+0x320)/2 // r/w 3-3 0x0 #define dmar_maskdsttran (dmacbase+0x328)/2 // r/w 3-3 0x0 #define dmar_maskerr (dmacbase+0x330)/2 // r/w 3-3 0x0 #define dmar_cleartfr (dmacbase+0x338)/2 // w 3 0x0 #define dmar_clearblock (dmacbase+0x340)/2 // w 3 0x0 #define dmar_clearsrctran (dmacbase+0x348)/2 // w 3 0x0 #define dmar_cleardsttran (dmacbase+0x350)/2 // w 3 0x0 #define dmar_clearerr (dmacbase+0x358)/2 // w 3 0x0 #define dmar_statusint (dmacbase+0x360)/2 // w 5 0x0 #define dmar_reqsrcreg (dmacbase+0x368)/2 // r/w 3-3 0x0 #define dmar_reqdstreg (dmacbase+0x370)/2 // r/w 3-3 0x0 #define dmar_sglreqsrcreg (dmacbase+0x378)/2 // r/w 3-3 0x0 #define dmar_sglreqdstreg (dmacbase+0x380)/2 // r/w 3-3 0x0 #define dmar_lstsrcreg (dmacbase+0x388)/2 // r/w 3-3 0x0 #define dmar_lstdstreg (dmacbase+0x390)/2 // r/w 3-3 0x0 #define dmar_dmacfgreg (dmacbase+0x398)/2 // r/w 1 0x0 #define dmar_chenreg (dmacbase+0x3a0)/2 // r/w 3-3 0x0 #define dmar_dmaidreg (dmacbase+0x3a8)/2 // r 32 #define dmar_dmatestreg (dmacbase+0x3b0)/2 // r/w 1 0x0 #define dmar_dmacid (dmacbase+0x3f8)/2 // r 64 0x0x44_57_11_10 #define dw_apb_wdt_base 0x1e400 #define wdt_cr (dw_apb_wdt_base + 0x00)/2 // r/w [4:0] 0x0 #define wdt_torr (dw_apb_wdt_base + 0x04)/2 // r/w [3:0] 0x7 #define wdt_ccvr (dw_apb_wdt_base + 0x08)/2 // r [31:0] 0x7fffff #define wdt_crr (dw_apb_wdt_base + 0x0c)/2 // r/w [7:0] 0x0 //0x76 #define wdt_stat (dw_apb_wdt_base + 0x10)/2 // r [0] 0x0
rock2 data sheet v1.1 08/04/06 rockchip electronics 121 of 128 #define wdt_eoi (dw_apb_wdt_base + 0x14)/2 // r [0] 0x0 #define wdtping_1bit_wr (wdt_cr)/2 #define dw_memctl_base 0x0000 #define memctl_sconr (dw_memctl_base + 0x00)/2 // r/w [31:0] 0x1c1168 #define memctl_stmg0r (dw_memctl_base + 0x04)/2 // r/w [31:0] 0x19d9451 #define memctl_stmg1r (dw_memctl_base + 0x08)/2 // r/w [31:0] 0x70008 #define memctl_sctlr (dw_memctl_base + 0x0c)/2 // r/w [31:0] 0x2009 #define memctl_srefr (dw_memctl_base + 0x10)/2 // r/w [31:0] 0x64 #define memctl_scslr0_low (dw_memctl_base + 0x14)/2 #define memctl_scslr0_high (dw_memctl_base + 0x34)/2 #define memctl_smskr0 (dw_memctl_base + 0x54)/2 // r/w [31:0] 0x80b #define memctl_smtmgr_set0 (dw_memctl_base + 0x94)/2 // r/w [31:0] 0x10441 #define memctl_smtmgr_set1 (dw_memctl_base + 0x98)/2 // r/w [31:0] 0x7c4f5b #define memctl_smtmgr_set2 (dw_memctl_base + 0x9c)/2 // r/w [31:0] 0x1c4f5b #define memctl_flash_trpdr (dw_memctl_base + 0xa0)/2 // r/w [31:0] 0xc8 #define memctl_smctlr (dw_memctl_base + 0xa4)/2 // r/w [31:0] 0x2480 #define memctlmemctl_ping_1bit_wr (memctl_sconr)/2 !///////// registers of apb register file ///////// #define i2dsp_txconf 0x1ec00/2 //w/r [5:0]; 6'h0; //i2dsp 0x1_ec00 #define i2dsp_txcom 0x1ec08/2 //w/r [2:0]; 3'h0; // tx_en,i1dsp_en,tx_dma_en #define i2dsp_txdb 0x1ec10/2 //w 16'h0; #define i2dsp_dpctrl 0x1ec20/2 //w/r [1:0]; 2'h0; // rxfiforst,txfiforst #define i2dsp_rxconf 0x1ec30/2 //w/r [5:0]; 6'h0; // [5:3]:fs,[2]:master,[1:0]:24-16bits #define i2dsp_rxcom 0x1ec34/2 //w/r [1:0]; 2'h0; // rx_en,i1dsp_en,rx_dma_en #define i2dsp_status 0x1ec38/2 //r [2:0]; 3'h0; // rxfifonemp,txfifonfull #define i2dsp_rxdb 0x1ec40/2 //r [2:0]; 3'h0; #define i2c_ext 0x1ec60/2 //w/r [1:0]; 2'h0; //i2dsp_ext,i2c_ext #define sw_codec_rstn 0x1ec64/2 //w/r [0]; 1'h0; //sw_codec_rstn #define pwm_tacmd 0x1ec84/2 //w/r [1:0]; 2'h0; //pwm 0x1_ec80 #define pwm_tadata0 0x1ec88/2 //w/r [15:0]; 16'h0; #define pwm_tadata1 0x1ec8c/2 //w/r [15:0]; 16'h0; #define pwm_tapre 0x1ec90/2 //w/r [9:0]; 10'h0; #define adc_adccon 0x1ed00/2 //w/r [4:0]; 5'h0; //adc 0x1_ed00 #define adc_adcdat0 0x1ed04/2 //r [9:0]; 10'h3ff #define adc_adcfre 0x1ed08/2 //w/r [7:0]; 8'h9; #define adc_adcrdy 0x1ed0c/2 //r [0]; 1'h1 #define dcdc_con0 0x1ed80/2 //w/r [2:0]; 3'h0; //dcdc 0x1_ed80 #define dcdc_con1 0x1ed88/2 //w/r [2:0]; 3'h0; #define clock_mclkcon 0x1ee00/2 //w/r [7:0]; 8'h1; //clock 0x1_ee00 #define clock_i2smclkcon 0x1ee04/2 //w/r [8:0]; 9'h107 #define clock_ahbclkcon 0x1ee08/2 //w/r [1:0]; 2'h0; #define clock_apbclkcon 0x1ee0c/2 //w/r [1:0]; 2'h0; #define clock_pll_ndiv 0x1ee10/2 //w/r [4:0]; 5'h6; #define clock_pll_mdiv 0x1ee14/2 //w/r [8:0]; 9'h1e; #define clock_pll_oddiv 0x1ee18/2 //w/r [1:0]; 2'h0; #define clock_pll_pdbp 0x1ee1c/2 //w/r [1:0]; 2'h1; #define clock_pll_bp 0x1ee1c/2 //w/r [1:0]; 2'h1; #define clock_pwrcon 0x1ee38/2 //w/r [2:0]; 3'h7;
rock2 data sheet v1.1 08/04/06 rockchip electronics 122 of 128 #define gpio_pcon0 0x1ee80/2 //w/r [15:0]; 16'b0; //gpio 0x1_ee80 #define gpio_pdat0 0x1ee88/2 //w/r [7:0]; 8'b0; #define gpio_pcon1 0x1ee90/2 //w/r [15:0]; 16'b0; #define gpio_pdat1 0x1ee98/2 //w/r [7:0]; 8'b0; #define gpio_pcon2a 0x1eea0/2 //w/r [15:0]; 16'b0; #define gpio_pcon2b 0x1eea4/2 //w/r [15:0]; 16'b0; #define gpio_pdat2 0x1eea8/2 //w/r [15:0]; 16'b0; #define gpio_pcon3 0x1eeb0/2 //w/r [15:0]; 16'b0; #define gpio_pdat3 0x1eeb8/2 //w/r [7:0]; 8'b0; #define gpio_extintr 0x1eec0/2 //w/r [7:0]; 8'b0; #define sdci_ctrl 0x1ef00/2 //w/r [4:0]; 5'h0; //sdmmc 0x1_ef00 #define sdci_dctrl 0x1ef04/2 //w/r [2:0]; 3'h0; #define sdci_dlen 0x1ef08/2 //w/r [15:0]; 16'h0; #define sdci_token 0x1ef0c/2 //w/r [7:0]; 8'h0; #define sdci_cmd 0x 1ef10/2 //w/r {[15:8],1'b0,[6:0]}; 16'h0; #define sdci_arg 0x1ef14/2 //w/r [31:0]; 32'h0; #define sdci_stac 0x1ef18/2 //w {[15:14],5'b0,[8:0]}; 16'h0; #define sdci_sta 0x1ef1c/2 //r [15:0]; 16'h3000; #define sdci_resp0 0x1ef20/2 //r [31:0]; 32'h0; #define sdci_resp1 0x1ef24/2 //r [7:0]; 8'h0; #define sdci_tx 0x1ef28/2 //w [31:0]; 32'h0; #define sdci_rx 0x1ef2c/2 //r [31:0]; 32'h0; #define sdci_crc16 0x1ef30/2 //r [15:0]; 32'h0; //codec i2c address #define p_add_aicr 0b00000000 //0x00 //w/r [7:0]; 8'h40//00 #define p_add_cr1 0b00 000010 //0x02 //w/r [7]r,[6:0]; 8'h08 #define p_add_cr2 0b000001 00 //0x04 //w/r [7]r,[6:0]; 8'h78//88 #define p_add_ccr 0b00000110 //0x06 //w/r [7:4],[2:0]; 8'h00 #define p_add_pmr1 0b00001000 //0x08 //w/r [7:0]; 8'h27//26 #define p_add_pmr2 0b00001010 //0x0a //w/r [7:3],[1:0]; 8'h00 #define p_add_cgr1 0b00001100 //0x0c //w/r [7:0]; 8'h00 #define p_add_cgr2 0b00001110 //0x0e //w/r [7:6],[4:0]; 8'h04 #define p_add_cgr3 0b00010000 //0x10 //w/r [4:0]; 8'h04 #define p_add_cgr4 0b00010010 //0x12 //w/r [7:6],[4:0]; 8'h04 #define p_add_cgr5 0b00010100 //0x14 //w/r [4:0]; 8'h04 #define p_add_cgr6 0b00010110 //0x16 //w/r [7:6],[4:0]; 8'h04 #define p_add_cgr7 0b00011000 //0x18 //w/r [4:0]; 8'h04 #define p_add_cgr8 0b00011010 //0x1a //w/r [7:6],[4:0]; 8'h0a #define p_add_cgr9 0b00011100 //0x1c //w/r [4:0]; 8'h0a #define p_add_cgr10 0b00011 110 //0x1e //w/r [7:0]; 8'h00 #define p_add_tr1 0b00100000 //0x20 //w/r [7:0]; 8'h00 #define p_add_tr2 0b00100010 //0x22 //w/r [7:0]; 8'hd8
rock2 data sheet v1.1 08/04/06 rockchip electronics 123 of 128 5 electrical characteristics 5.1 absolute maximum ratings absolute maximum ratings parameter min max units ambient operating temperature -10 80 c storage temperature -40 120 c vddpll -0.3 2.0 v vcc -0.3 3.6 v input voltage on usb dm, dp pins (usbio) -0.3 3.6 v input voltage on any digital i/0 pin relative to ground -0.3 vcc+0.3 v input voltage on any analog pin relative to ground -0.3 vdda+0.3 v 5.2 operating conditions table 11: recommended operation conditions. parameter min typ max units digital core supply voltage -- vdd 1.6 1.8 2.0 v digital i/o supply voltage ? vcc 2.6 2.9 3.3 v analog supply voltage ? vdda 1.6 1.8 2.0 v analog hp-amp supply voltage ? vddao 1.6 1.8 2.0 v 10bit adc supply voltage ? vcca 2.6 2.9 3.3 v usb supply voltage ? vcca 2.6 2.9 3.3 v usb supply voltage ? vdda (generate internal) 1.6 1.8 2.0 v
rock2 data sheet v1.1 08/04/06 rockchip electronics 124 of 128 5.3 dc characteristics operating conditions: v cc = 3.0v 0.3v, v dd = 1.8v 0.2v, tj = - 40 to + 120 c. parameter symbol min typ max unit quiescent supply current, v i = v dd or v ss i dds ma high level output voltage ( 2ma) v oh 0.8xvcc v low level output voltage (2ma) v ol 0.2xvcc v high level input voltage 3v buffers v ih 0.7vcc vcc+0.6 v low level input voltage 3v buffers v il -0.3 0.4vcc v input leakage current ili 10 a output leakage current ilo 5 a gpio drive 8 ma operating supply current, fclk=12mhz, ta=25 o c, vcc=3.0v, vdd=1.8v ivdd 35 50 ma 5.4 ac characteristics line input to adc measurement conditions: t = 25c, vdda = vddao = vrefp = 1.8v, input sine wave with a frequency of 1khz, fmclk = 12mhz, fs = 48khz, measurement bandwidth 20hz ? 20khz, unless otherwise specified. parameter test conditions min. typ max. unit input level full scale, gain gil, gir = 0db (note 1) 1.34 1.53 1.72 vpp snr a-weighted, 1khz sine wave @ full scale and gain gil, gir = 0db 80 85 db thd 1khz sine wave @ full scale ?1db and gain gil, gir = 0db -85 -80 db dynamic range a-weighted, 1khz sine wave @ full scale ?60db and gain = 0db (note 2) 80 85 db psrr 100mvpp 1khz sinewave is applied to vdda, input data is 0 and gain gil, gir = 0db 50 db gain range gil, gir 4-bit programmable range, @1khz 0 22.5 db gain step gil, gir 1.5 db gain accuracy gil, gir @1khz -1 +1 db
rock2 data sheet v1.1 08/04/06 rockchip electronics 125 of 128 input resistance 30 40 50 kohm input capacitance includes 10pf for esd, bonding and package pins capacitances 25 pf input bypass capacitor cbyline 1 uf gain gil, gir = 0db, without high pass filter 200 gain gil, gir = 22.5db, without hpf -2000 +2000 offset (note 3) gain gil, gir = 0 or 22.5db, with hpf -4 +4 lsb note 1: the full scale input voltage scales with vdda, equals to 0.85*vref (typ) note 2: the specified value is extrapolated by adding 60db to the measured snr note 3: with 1 lsb = 55v for a 16-bit word and vref=1.8v microphone input to adc measurement conditions: t = 25c, vdda = vddao = vrefp = 1.8v, input sine wave with a frequency of 1khz, fmclk = 12mhz, fs = 48khz, measurement bandwidth 20hz ? 20khz, unless otherwise specified. parameter test conditions min. typ max. unit input level full scale, gain gil, gir = 0db, boost gain gim = 20db (note 1) 0.134 0.153 0.172 vpp a-weighted, 1khz sine wave @ full scale and gain gil, gir = 0db, boost gain gim = 0db 80 85 db snr a-weighted, 1khz sine wave @ full scale and gain gil, gir = 0db, boost gain gim = 20db 70 75 db thd 1khz sine wave @ full scale ?1db and -65 -60 gain gil, gir = 0db, boost gain gim = 20db db a-weighted, 1khz sine wave @ full scale ?60db and gain gil, gir = 0db, boost gain gim = 0db (note 2) 80 85 db dynamic range a-weighted, 1khz sine wave @ full scale ?60db and gain gil, gir = 0db, boost gain gim = 20db (note 2) 70 75 db
rock2 data sheet v1.1 08/04/06 rockchip electronics 126 of 128 psrr 100mvpp 1khz sinewave is applied to vdda, input data is 0 and gain gil, gir = 0db, boost gain gim = 20db 50 db gain boost boost gain gm when activated 20 db input resistance gain gil, gir = 0 or 22.5db, boost gain gim = 20db 14 20 26 kohm input capacitance includes 10pf for esd, bonding and package pins capacitances 25 pf input bypass capacitor cbymic 1 uf gain gil, gir = 0db, boost gain gim = 20db, without high pass filter 1500 gain gil, gir = 22.5db, boost gain gim = 20db, without hpf -13e3 +13e3 offset (note 3) gain gil, gir = 0 or 22.5db, boost gain gim = 20db, with hpf -2 +2 lsb note 1: the full scale input voltage scales with vdda, equals to 0.085*vref (typ) note 2: the specified value is extrapolated by adding 60db to the measured snr note 3: with 1 lsb = 55v for a 16-bit word and vref=1.8v dac to headphone output measurement conditions: t = 25c, vdda = vddao = vrefp = 1.8v, input sine wave with a frequency of 1khz, fmclk = 12mhz, fs = 48khz, measurement bandwidth 20hz ? 20khz, unless otherwise specified. parameter test conditions min. typ max. unit output level full scale, gain gol,gor,godl, godr = 0db (note 1) 1.34 1.53 1.72 vpp rl = 16 ohm 18 maximum power output rl = 32 ohm 9 mw snr 85 90 a-weighted, 1khz sine wave @ full scale and gain gol,gor,godl, godr = 0db db thd 1khz sine wave @ full scale ? 1db and gain gol,gor,godl,godr = 0db, 16 ohm load -65 -60 db
rock2 data sheet v1.1 08/04/06 rockchip electronics 127 of 128 1khz sine wave @ full scale ? 1db and gain gol,gor,godl,godr = 0db, 10kohm load -85 -80 dynamic range a-weighted, 1khz sine wave @ full scale ?60db and gain gol, gor,godl,godr = 0db (note 2) 85 90 db psrr 100mvpp 1khz sinewave is applied to vdda, input data is 0 and gain gol,gor,godl,godr = 0db 50 db channel separation 16 ohm loads @1khz, aom and aoms have to be connected together as close as possible of the headphone connector 65 db gain range gol, gor 5-bit programmable range, mixed analog/digital control, @1khz -32 +6 db gol, gor: +6 db ~ +2 db 0.5 gol, gor: +2 db ~ -10 db 1 gain step gol, gor: -10 db ~ -32 db 2 db gain accuracy gol, gor @1khz -1 +1 db gain range godl, godr 4-bit programmable range, mixed analog/digital control, @1khz -22.5 +0 db gain step godl, godr 1.5 db gain accuracy godl, godr @1khz -1 +1 db output resistance rl 16 ohm output capacitance cp 100 pf output bypass capacitor cl (rl = 10 kohm) 1 uf offset error gain gol,gor,godl,godr = 0db -50 +50 mv note 1: the full scale output voltage scales with vdda, equals to 0.85*vref (typ) note 2: the specified value is extrapolated by adding 60db to the measured snr
rock2 data sheet v1.1 08/04/06 rockchip electronics 128 of 128 5.5 package & dimensions 5.5.1 packaging type 128/100 pins lqfp package 5.5.2 demensions 128/100: 14mm x 14mm 5.5.3 marking following markings are printed on the package of the asic manufacturer: rockchip customer markings: rock260x manufacturer part number: lot code:

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